LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF

• US 20130328129A1
• Filed: 08/19/2013
• Published: 12/12/2013
• Est. Priority Date: 04/12/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Ranade, Pushkar, Thompson, Scott E., Sonkusale, Sachin R., Zhang, Weimin
• Granted Patent: US 9,496,261 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV_T compared to conventional bulk CMOS and can allow the threshold voltage V_T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Claims

1. An integrated circuit having transistor devices of a plurality of device types formed on a substrate, comprising:

a first screening layer for a first digital device, the first screening layer being positioned below a first gate of the first digital device, the first screening layer having a first dopant concentration between 1×

10¹⁸ to 1×

10²⁰ atoms/cm³;

a second screening layer for a second device type, the second screening layer being positioned below a second gate of the second device type, the second screening layer having a second dopant concentration between 5×

10¹⁸ to 5×

10²⁰ atoms/cm³;

an epitaxially grown layer forming a common epitaxial layer for the first digital device and the second device type, the common epitaxial layer being positioned above and adjacent to the first screening layer and the second screening layer,

wherein at least a portion of the common epitaxial layer is maintained as a substantially undoped channel region for the first digital device, the substantially undoped channel region of the first digital device having a first dopant concentration less than 5×

10¹⁷ atoms/cm³; and

a shallow trench isolation between the first digital device and the second device type, the shallow trench isolation formed by etching the common epitaxial layer to form a trench and depositing a dielectric within the trench, the shallow trench isolation being formed after forming the common epitaxial layer, wherein the shallow trench isolation extends beyond the first screening layer and the second screening layer.

2. The integrated circuit of claim 1, wherein the first screening layer is formed by ion implanting the first screening layer into the substrate, and wherein the second screening layer is formed by implanting the second screening layer into the substrate.

3. The integrated circuit of claim 2, wherein the first screening layer and the second screening layer are both exposed to a low temperature recrystallization anneal.

4. The integrated circuit of claim 3, wherein the low temperature crystallization anneal is performed at a temperature range of 550°

C. to 600°

C.

5. The integrated circuit of claim 2, wherein the a high temperature anneal is performed after implanting the first screening layer and the second screening layer, and further including an oxide layer on the substrate that is temporarily formed after performing the high temperature annealing, wherein the oxide layer is stripped before performing the epitaxial deposition to form the common epitaxial layer.

6. The integrated circuit of claim 5, wherein the oxide layer comprises a thin oxide layer formed on the substrate.

7. The integrated circuit of claim 1, wherein the first screening layer for the first digital device further includes a first P-type screening layer for a first transistor element of the first digital device, and a first N-type screening layer for a second transistor element of the first digital device.

8. The integrated circuit of claim 7, further comprising:

a body tap operable to apply a body bias voltage to the transistor element of the first digital device.

9. The integrated circuit of claim 1, wherein the second screening layer for the second device type further includes a second P-type screening layer for a first transistor element of the second device type, and a second N-type screening layer for a second transistor element of the second device type.

10. The integrated circuit of claim 1, wherein the first screening layer and the second screening layer are formed using a process that includes performing a diffusion prevention treatment.

11. The integrated circuit of claim 10, wherein the performing the diffusion prevention treatment further comprises implanting at least one of indium and carbon.

12. The integrated circuit of claim 10, wherein the performing the diffusion prevention treatment further comprises forming a semiconductor layer between the screening layer and the common epitaxial layer.

13. The integrated circuit of claim 12, wherein the semiconductor layer includes carbon.

14. The integrated circuit of claim 12, wherein the semiconductor layer further includes SiGe deposited before forming the common epitaxial layer.

15. The integrated circuit of claim 1, wherein the second device type is a digital legacy device having post-epitaxial deposition channel implants to provide legacy transistor functionality.

16. The integrated circuit of claim 1, wherein the second device type is an analog device.

17. The integrated circuit of claim 9, further comprising:

a P-type well for the first transistor element of the second device type;

an N-type well for the second transistor element of the second device type;

a P-type layer formed over the second P-type screening layer, wherein the P-type layer operates as a first threshold voltage control layer for the first transistor element of the second device type; and

an N-type layer formed over the second N-type screening layer, wherein the N-type layer operates as a second threshold voltage control layer for the second transistor element of the second device type.

18. The integrated circuit of claim 17, further comprising:

a body tap to at least one of the P-type and N-type wells, the body tap being operable to apply a bias voltage to the transistor body.

19. The integrated circuit of claim 1, further comprising:

one of a single, double, or triple gate oxidation layers for each device.