WAFER-LEVEL FLIP CHIP DEVICE PACKAGES AND RELATED METHODS

• US 20130328172A1
• Filed: 03/04/2013
• Published: 12/12/2013
• Est. Priority Date: 06/07/2012
• Status: Active Grant

• Current Assignee: Cooledge Lighting Inc.
• Original Assignee: Cooledge Lighting Inc.
• Inventors: Tischler, Michael A.
• Granted Patent: US 9,231,178 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0568 Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/27003 for holding or transferring the layer preform
• CPC Class Codes: H01L 2224/27436 : Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/29082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 : Fillers
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0041 : relating to wavelength conversion elements
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/505 : characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.

Claims

1. A method of fabricating an electronic device, the method comprising:

providing a wafer comprising a plurality of semiconductor layers;

forming a plurality of electrical contacts on a surface of the wafer, each electrical contact being in direct contact with at least one of the semiconductor layers thereunder, thereby defining a plurality of unsingulated chips each comprising a plurality of the electrical contacts;

thereafter, and without formation of a metallic or conductive layer on the electrical contacts therebetween, applying an anisotropic conductive adhesive (ACA) onto the surface of the wafer and in direct contact with each of the electrical contacts;

thereafter, singulating the wafer into individual chips, each chip comprising first and second electrical contacts with the ACA thereover;

providing a substrate having first and second conductive traces on a first surface thereof in a bonding region, the first and second conductive traces being separated by a gap therebetween;

positioning first and second electrical contacts of one of the chips over the first and second conductive traces, a portion of the ACA being disposed between the electrical contacts and the traces; and

bonding the first and second electrical contacts of the chip to the first and second traces, respectively, thereby establishing electrical connection between at least one of (i) the first electrical contact and the first trace or (ii) the second electrical contact and the second trace, but without electrically bridging the traces together or electrically bridging the electrical contacts together.

2. The method of claim 1, wherein the ACA comprises an anisotropic conductive film.

3. The method of claim 2, wherein applying the ACA onto the surface of the wafer comprises laminating the anisotropic conductive film to the wafer.

4. The method of claim 1, wherein, for each unsingulated chip, the top surface of each of the plurality of electrical contacts is absolutely coplanar with or recessed below the surface of the chip surrounding the electrical contact.

5. The method of claim 1, wherein, for each unsingulated chip, the top surface of each of the plurality of electrical contacts is recessed below the surface of the chip surrounding the electrical contact by more than 3 μ

m.

6. The method of claim 1, wherein forming the plurality of electrical contacts over the surface of the wafer comprises only a single deposition step.

7. A composite wafer comprising:

a semiconductor substrate comprising a plurality of at least partially unsingulated chips, each chip comprising (i) a plurality of exposed electrical contacts and (ii) a non-contact region disposed between the electrical contacts, a top surface each of the electrical contacts being substantially coplanar with or recessed below a surface of the non-contact region disposed around the electrical contact; and

an anisotropic conductive adhesive (ACA) on the semiconductor substrate, including the electrical contacts and the non-contact region of each chip.

8. The wafer of claim 7, further comprising a plurality of trenches extending through only a portion of a thickness of the substrate and partially singulating the chips.

9. The wafer of claim 8, wherein a portion of the ACA is disposed over each of the trenches.

10. The wafer of claim 8, wherein the ACA comprises discrete portions separated approximately along the trenches.

11. The wafer of claim 7, wherein the ACA comprises an anisotropic conductive film.

12. The wafer of claim 7, wherein each chip comprises a light-emitting diode (LED) die.

13. The wafer of claim 12, wherein each LED die comprises an inorganic LED die.

14. The wafer of claim 13, wherein at least a portion of each LED die comprises a semiconductor material comprising at least one of silicon, GaAs, InAs, AlAs, InP, GaP, AlP, InSb, GaSb, AlSb, GaN, InN, AN, SiC, ZnO, or an alloy or mixture thereof.

15. The wafer of claim 7, wherein each chip comprises a laser.

16. The wafer of claim 7, wherein a thickness of the ACA across the semiconductor substrate is substantially uniform.

17. The wafer of claim 7, wherein, for each at least partially unsingulated chip, the top surface of each of the plurality of electrical contacts is absolutely coplanar with or recessed below the surface of the chip surrounding the electrical contact.

18. The wafer of claim 7, wherein, for each at least partially unsingulated chip, the top surface of each of the plurality of electrical contacts is recessed below the surface of the chip surrounding the electrical contact by more than 3 μ

m.

19. The wafer of claim 7, wherein, for each at least partially unsingulated chip, each of the plurality of electrical contacts is in direct physical contact with (i) a semiconductor portion of the wafer thereunder and (ii) the ACA.