MANAGING PAGE TABLE ENTRIES

• US 20130339651A1
• Filed: 06/14/2012
• Published: 12/19/2013
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bybell, Anthony J., Gschwind, Michael K.
• Granted Patent: US 9,753,860 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions

Abstract

Embodiments relate to managing page table entries in a processing system. A first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses is identified. The page table includes a second page table entry contiguous with the second page table entry. It is determined whether the first PTE may be joined with the second PTE, based on the respective pages of main storage being contiguous. A marker is set in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.

Claims

1. A computer program product for managing page table entries in a processing system, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry;

determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous; and

setting a marker in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.

2. The computer program product of claim 1, further comprising performing an address translation of a virtual address comprising:

based on the virtual address, obtaining the first PTE; and

based on the marker, using the first PTE to translate virtual addresses to both the first page and the second page absent accessing the second PTE.

3. The computer program product of claim 1, wherein the method further comprises executing a translation lookaside buffer (TLB) invalidate instruction for invalidating TLB entries associated with the first PTE and second PTE.

4. The computer program product of claim 1, wherein the method further comprises starting a memory access routine for the first virtual address stored in the first page table entry (PTE) in the page table, wherein the memory access routine performs:

locating the first PTE in the page table;

determining with the processor whether the marker associated with the first PTE is set;

identifying a large page size of a large page associated with the page table based on determining that the marker is set in the first PTE, wherein the large page consisting of contiguous pages comprising said first page and said second page;

identifying a third PTE that points to a start location of the large page based on determining that the marker associated with the first PTE is set; and

obtaining a physical address of the large page of main storage identified by the third PTE that points to a start location of the page based on determining that the marker associated with the first PTE is set.

5. The computer program product of claim 4, wherein the method further comprises:

storing translation information, marker information and said physical address in a TLB; and

using said stored translation information to translate virtual addresses associated with the large page.

6. The computer program product of claim 1, wherein the marker is set in a plurality of PTEs indicating the main storage pages identified by the plurality of PTEs are contiguous, the plurality of PTEs comprising each of the first PTE and the second PTE.

7. The computer program product of claim 1, wherein the PTEs are any one of third PTEs in page tables of a hierarchy of translation tables, or fourth PTEs in a group of PTEs, each fourth PTE having a field identifying an associated virtual address.

8. A computer system for accessing a memory location, the system comprising:

a memory; and

a processor coupled to the memory, the computer system configured to perform a method comprising;

identifying, with the processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry;

determining, with the processor, whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous; and

setting a marker in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous.

9. The system of claim 8, wherein the method the method further comprises performing an address translation of a virtual address comprising:

based on the virtual address, obtaining the first PTE; and

based on the marker, using the first PTE to translate virtual addresses to both the first page and the second page absent accessing the second PTE.

10. The system of claim 8, wherein the method further comprises executing a translation lookaside buffer (TLB) invalidate instruction for invalidating TLB entries associated with the first PTE and second PTE.

11. The system of claim 8, wherein the method further comprises starting a memory access routine for the first virtual address stored in the first page table entry (PTE) in the page table, wherein the memory access routine performs:

locating the first PTE in the page table;

determining with the processor whether the marker associated with the first PTE is set;

identifying a large page size of a large page associated with the page table based on determining that the marker is set in the first PTE, wherein the large page consisting of contiguous pages comprising said first page and said second page;

identifying a third PTE that points to a start location of the large page based on determining that the marker associated with the first PTE is set; and

obtaining a physical address of the large page of main storage identified by the third PTE that points to a start location of the page based on determining that the marker associated with the first PTE is set.

12. The system of claim 11, wherein the method further comprises:

storing translation information, marker information and said physical address in a TLB; and

using said stored translation information to translate virtual addresses associated with the large page.

13. The system of claim 8, wherein the marker is set in a plurality of PTEs indicating the main storage pages identified by the plurality of PTEs are contiguous, the plurality of PTEs comprising each of the first PTE and the second PTE.

14. The system of claim 8, wherein the PTEs are any one of third PTEs in page tables of a hierarchy of translation tables, or fourth PTEs in a group of PTEs, each fourth PTE having a field identifying an associated virtual address.

15-20. -20. (canceled)