UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE

• US 20140001555A1
• Filed: 06/29/2012
• Published: 01/02/2014
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Haran, Balasubramanian S., Ponoth, Shom, Standaert, Theodorus E., Yamashita, Tenko
• Granted Patent: US 9,214,378 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

Claims

1. A method of making a silicon-on-insulator (SOI) semiconductor device, comprising:

etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer;

filling the undercut isolation trench with an undercut fill comprising an insulating material to form an undercut isolation region;

forming a field effect transistor (FET) device on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

2. The method of claim 1, wherein etching the undercut isolation trench comprises:

etching a shallow shallow trench isolation (STI) region into the SOI substrate; and

isotropically etching the bottom substrate on the sides of the shallow STI region such that the undercut isolation trench extends into the bottom substrate under the BOX layer.

3. The method of claim 1, further comprising oxidizing a portion of the bottom substrate to form an oxidized region inside the undercut isolation trench before filling the undercut isolation trench.

4. The method of claim 1, further comprising forming an undercut isolation region liner over an interior surface of the undercut isolation trench before filling the undercut isolation trench, such that the undercut isolation region liner is located between the undercut fill and the bottom substrate.

5. The method of claim 4, wherein the undercut isolation region liner is formed over an oxidized region of the bottom substrate inside the undercut isolation trench.

6. The method of claim 4, wherein the undercut isolation region liner comprises one of hafnium oxide and nitride.

7. The method of claim 1, wherein the undercut fill comprises oxide.

8. The method of claim 1, further comprising etching into the undercut isolation region and the bottom substrate to form a deep STI region, wherein the deep STI region extends deeper into the bottom substrate than the undercut isolation region.

9. The method of claim 8, wherein the deep STI region comprises an insulating fill material that is different from the undercut fill.

10. The method of claim 8, wherein the etch to form the deep STI region additionally etches through an undercut isolation region liner located between the undercut fill and the bottom substrate.

11. The method of claim 1, further comprising removing a pad nitride layer located on the top SOI layer before forming the FET device on the top SOI layer.

12. The method of claim 1, further comprising forming a source/drain contact to the source/drain region of the FET, wherein the source/drain contact extends into the undercut isolation region, and wherein the source/drain contact is separated from the bottom substrate by the undercut fill.

13. A silicon-on-insulator (SOI) semiconductor device, comprising:

an SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer;

a field effect transistor (FET) device located on the top SOI layer; and

an undercut isolation region located in the SOI substrate adjacent to the FET device, wherein the undercut isolation region extends through the top SOI layer and the BOX layer and into the bottom substrate underneath the BOX layer, such that a portion of the undercut isolation region is underneath a source/drain region of the FET, wherein the undercut isolation region comprises an undercut fill comprising an insulating material.

14. The device of claim 13, further comprising an oxidized region in the bottom substrate located between the undercut isolation region and the bottom substrate.

15. The device of claim 13, wherein the undercut isolation region further comprises an undercut isolation region liner located between the undercut fill and the bottom substrate.

16. The device of claim 15, wherein the undercut isolation region liner comprises one of hafnium oxide and nitride.

17. The device of claim 13, wherein the undercut fill comprises oxide.

18. The device of claim 13, further comprising a deep STI region located in the undercut isolation region, wherein the deep STI region extends deeper into the bottom substrate than the undercut isolation region.

19. The device of claim 18, wherein the deep STI region comprises an insulating fill material that is different from the undercut fill.

20. The device of claim 13, further comprising a source/drain contact to the source/drain region of the FET, wherein the source/drain contact extends into the undercut isolation region, and wherein the source/drain contact is separated from the bottom substrate by the undercut fill.