Compact High Speed Sense Amplifier for Non-Volatile Memory and Hybrid Lockout
First Claim
1. A sense amplifier for a memory circuit, comprising:
- an intermediate circuit, including a first node selectively connectable to one or more bit lines;
bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines;
a pre-charge switch by which the first node can be connected to a first supply level for pre-charging of the first node for a sensing operation;
a first latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node;
a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; and
first and second switches whereby the value latched in the first and second latch circuits can respectively be transferred to a data bus,wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits can sequentially be connected to have the value latched therein set according to the level of the first node.
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Accused Products
Abstract
A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit uses one power supply level for the bit line driving path and a second supply level for a data latch of the sense amp. The latch'"'"'s supply level is of a high level that used for driving the bit lines and can be provided by a charge pump. The sense amp need use only NMOS devices for its analog path. For balancing performance and current consumption, the sense amp also includes an additional latch to support a “hybrid lockout” sensing mode, where in a verify operation a read-lockout is used between different data states, but not between the low and high quick pass write (QPW) verifies.
36 Citations
18 Claims
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1. A sense amplifier for a memory circuit, comprising:
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an intermediate circuit, including a first node selectively connectable to one or more bit lines; bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines; a pre-charge switch by which the first node can be connected to a first supply level for pre-charging of the first node for a sensing operation; a first latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; a second latch circuit connectable to the intermediate circuit to have a value latched therein set according the level on the first node; and first and second switches whereby the value latched in the first and second latch circuits can respectively be transferred to a data bus, wherein, in a sensing operation, after pre-charging the first node and prior to a subsequent pre-charging, the first and second data latch circuits can sequentially be connected to have the value latched therein set according to the level of the first node. - View Dependent Claims (2, 3, 4, 5, 7)
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6. The sense amplifier of claim 6, wherein a node of the first latch that holds the inverted version of the value latched therein is connectable to the first node through a fourth switch.
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8. A sense amplifier for a memory circuit, comprising:
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an intermediate circuit, including a first node selectively connectable to one or more bit lines; a first latch circuit selectively connectable to the first node; bit line selection circuitry connected to the first node, whereby the first node can selectively be connected to one or more bit lines; a first switch whereby the first latch circuit can be connected to a data bus; a second switch whereby the first node is selectively connectable to a first voltage supply level; and a third switch whereby the first node is selectively connectable to an external node, wherein the path between the external node and the first node is formed of only n-type devices, and wherein when a value held in the first latch circuit is at a high value the first node is cut off from the first voltage supply level, and when the value held in the first latch circuit is at a low value the first node is cut off from the external node. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification