CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES

• US 20140006888A1
• Filed: 09/09/2013
• Published: 01/02/2014
• Est. Priority Date: 11/23/1999
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Rajski, Janusz, Tyszer, Jerzy, Kassab, Mark, Mukherjee, Nilanjan
• Granted Patent: US 9,134,370 B2
• Time in Patent Office: Days
• US Class Current: 714/727
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Claims

1-5. -5. (canceled)

6. A circuit, comprising:

a register; and

a decompressor comprising a phase shifter and a linear feedback shift register (LFSR), the LFSR being coupled between an output of the register and an input of the phase shifter,

the register being configured to load compressed test pattern bits and apply the compressed test pattern bits to the LFSR of the decompressor, and

the decompressor being configured to decompress the compressed test pattern bits into decompressed test pattern bits.

7. The circuit of claim 7, wherein the register is coupled to automatic testing equipment (ATE) located externally to the circuit.

8. The circuit of claim 7, further including scan chains coupled to the phase shifter.

9. The circuit of claim 7, wherein the phase shifter is formed from only XOR gates.

10. The circuit of claim 7, wherein the register is coupled to automatic testing equipment (ATE) located externally to the circuit, the register being configured to load the compressed test pattern from the ATE and output the compressed test pattern to the LFSR.

11. The apparatus of claim 7, wherein the register is a shift register.

12-17. -17. (canceled)