DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING

• US 20140008809A1
• Filed: 09/12/2013
• Published: 01/09/2014
• Est. Priority Date: 12/30/2011
• Status: Active Grant

• Current Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Original Assignee: Deca Technologies Incorporated (Infineon Technologies AG)
• Inventors: Scanlan, Christopher M.
• Granted Patent: US 8,922,021 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3164 : the coating being a foil
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer.

Claims

1. A method of making a semiconductor package, comprising:

placing a plurality of die units face up on a carrier, each die unit having an active front surface oriented away from the carrier and a back surface opposing the active front surface, the active front surface and the back surface joined by at least four side surfaces;

forming at least one conductive interconnect coupled to each of the plurality of die units; and

encapsulating the plurality of die units and the at least one conductive interconnects with an encapsulant that covers the active front surface and the at least four side surfaces of each of the plurality of die units.

2. The method of claim 1, further comprising encapsulating the plurality of die units and the at least one conductive interconnects in a single step.

3. The method of claim 1, further comprising exposing the at least one conductive interconnect through removal of a portion of the encapsulant covering the active front surface.

4. The method of claim 1, further comprising forming the encapsulant as a polymer layer or dielectric film positioned between the plurality of die units and the carrier.

5. The method of claim 1, further comprising disposing a dielectric film over the back surface of the plurality of die units comprising a thickness between a ratio of 5:

1 and 1;

5 compared with a thickness of the encapsulant covering the active front surface.

6. The method of claim 1, further comprising encapsulating the plurality of die units with a compression molding process or lamination process.

7. The method of claim 1, further comprising forming the at least one conductive interconnect as plated post.

8. The method of claim 7, further comprising coupling the plated post to a redistribution layer.

9. A method of making a semiconductor package, comprising:

providing a die unit comprising an active front surface opposite a back surface, the active front surface and the back surface joined by at least four side surfaces;

forming a conductive interconnect coupled to the active front surface;

disposing the die unit over a carrier with the active front surface oriented away from the carrier; and

encapsulating the die unit and the conductive interconnect with an encapsulant that covers the active front surface and the at least four side surfaces of the die unit.

10. The method of claim 9, further comprising encapsulating the die unit and the conductive interconnect with the encapsulant in a single step.

11. The method of claim 9, further comprising exposing the conductive interconnect through removing a portion of the encapsulant.

12. The method of claim 9, further comprising encapsulating the die unit and the conductive interconnect before removing the carrier.

13. The method of claim 9, wherein the conductive interconnect has a height of at least about 20 microns.

14. The method of claim 9, further comprising forming a fan-in redistribution layer over the die unit before encapsulating the die unit.

15. The method of claim 9, further including forming the conductive interconnect as a copper post plated over a pad on the active front surface of the die unit.

16. The method of claim 9, further comprising forming the conductive interconnect coupled to a fan-in or fan-out redistribution layer.

17. A semiconductor package comprising:

a die unit having an active surface and a back surface opposing the active surface, the active surface and back surface joined by at least four side surfaces;

a first encapsulant that covers the active surface and the at least four side surfaces of the die unit; and

a plurality of conductive interconnects electrically connecting a plurality of die bond pads on the active surface to a first redistribution layer.

18. The semiconductor package of claim 17, further comprising a second encapsulant disposed over the back surface of the die unit.

19. The semiconductor package of claim 18, wherein the first redistribution layer is a fan-out redistribution layer formed over the first encapsulant.

20. The semiconductor package of claim 19, further comprising a second redistribution layer formed over the active surface of the die unit, wherein the conductive interconnects are plated over the second redistribution layer.

21. The semiconductor package of claim 18, wherein the conductive interconnects are plated over the plurality of die bond pads on the active surface of the die unit.

22. The semiconductor package of claim 18, further including a polymer layer or dielectric film disposed over the active surface.

23. The semiconductor package of claim 22, wherein the first redistribution layer is a fan-in redistribution layer formed over the polymer layer or dielectric film.

24. The semiconductor package of claim 18, wherein a thickness of the first encapsulant covering the active surface is substantially a same thickness as a thickness of the second encapsulant covering the back surface.

25. The semiconductor package of claim 24, wherein a thickness of the first encapsulant covering the active surface has a ratio of between approximately ⅕

and 5 in relation to a thickness of the second encapsulant covering the back surface.

26. The semiconductor package of claim 18, wherein the conductive interconnects have a height of at least about 20 microns.

27. The semiconductor package of claim 18, wherein the first encapsulant or the second encapsulant comprise an epoxy film.