CIRCUITS, DEVICES, METHODS AND APPLICATIONS RELATED TO SILICON-ON-INSULATOR BASED RADIO-FREQUENCY SWITCHES

• US 20140009214A1
• Filed: 07/06/2013
• Published: 01/09/2014
• Est. Priority Date: 07/07/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Altunkilic, Fikret, Blin, Guillaume Alexandre, Cebi, Haki, Fuh, Hanching, Madan, Anuj, Srirattana, Nuttapong, Sprinkle, Steven Christopher, Hsu, Mengshu, Lee, Jong-Hoon, Shih, Chuming
• Granted Patent: US 9,160,328 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

Claims

1. A radio-frequency (RF) switch comprising:

a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body; and

a compensation network including a gate-coupling circuit that couples the gates of each pair of neighboring FETs, the compensation network further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

2. The switch of claim 1 wherein at least some of the FETs are silicon-on-insulator (SOI) FETs.

3. The switch of claim 1 wherein the gate-coupling circuit includes a capacitor.

4. The switch of claim 3 wherein the gate-coupling circuit further includes a resistor in series with the capacitor.

5. The switch of claim 1 wherein the gate-coupling circuit includes a resistor.

6. The switch of claim 1 wherein the body-coupling circuit includes a capacitor.

7. The switch of claim 6 wherein the body-coupling circuit further includes a resistor in series with the capacitor.

8. The switch of claim 1 wherein the body-coupling circuit includes a resistor.

9. (canceled)

10. A semiconductor die comprising:

a semiconductor substrate;

a plurality of field-effect transistors (FETs) formed on the semiconductor substrate and connected in series, each FET including a gate and a body; and

a compensation network formed on the semiconductor substrate, the compensation network including a gate-coupling circuit that couples the gates of each pair of neighboring FETs, the compensation network further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

11. The die of claim 10 further comprising an insulator layer disposed between the FETs and the semiconductor substrate.

12. The die of claim 11 wherein the die is a silicon-on-insulator (SOI) die.

13. A method for fabricating a semiconductor die, the method comprising:

providing a semiconductor substrate;

forming a plurality of field-effect transistors (FETs) on the semiconductor substrate so as to be connected in series, each FET having a gate and a body;

forming a gate-coupling circuit on the semiconductor substrate to couple the gates of each pair of neighboring FETs; and

forming a body-coupling circuit on the semiconductor substrate to couple the bodies of each pair of neighboring FETs.

14. The method of claim 13 further comprising forming an insulator layer between the FETs and the semiconductor substrate.

15-20. -20. (canceled)