METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20140011303A1
• Filed: 09/05/2012
• Published: 01/09/2014
• Est. Priority Date: 07/03/2012
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Meng, Lingkuan
• Granted Patent: US 8,728,948 B2
• Time in Patent Office: Days
• US Class Current: 438/8
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate stack on a substrate;

depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and

etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively.

2. The method according to claim 1, wherein etching the second dielectric layer and the first dielectric layer comprises:

performing a main etching operation on the second dielectric layer to form the second spacer, with a remainder of the second dielectric layer left on the first dielectric layer;

performing an over etching operation to remove the remainder of the second dielectric layer; and

performing etching to remove exposed portions of the first dielectric layer on the substrate.

3. The method according to claim 1, wherein the gate stack comprises a gate dielectric layer and a gate electrode layer, wherein the gate electrode layer comprises any of polysilicon, amorphous silicon, and a metal gate, and the gate dielectric layer comprises any of silicon oxide, silicon nitroxide, and a high K material.

4. The method according to claim 1, wherein the first dielectric layer comprises silicon oxide, and depositing thereof comprises RTO, PECVD, or SACVD.

5. The method according to claim 1, wherein the second dielectric layer comprises silicon nitride or diamond-like amorphous carbon, and depositing thereof comprises LPCVD or PECVD.

6. The method according to claim 1, wherein the etching adopts etching gases including a fluorine-based gas, an oxidizing gas and a helium-based gas.

7. The method according to claim 6, wherein the main etching operation comprises adjusting an electrode power, a chamber pressure, and a ratio of flow rates of the reactive gases to enhance anisotropy so as to achieve the spacer with a steep profile.

8. The method according to claim 6, wherein the over etching operation comprises adjusting an electrode power, a chamber pressure, and a ratio of flow rates of the reactive gases to achieve a great etching selection ratio of the dielectric layer with respect to the substrate.

9. The method according to claim 8, wherein the etching selectivity is greater than 10:

1.

10. The method according to claim 6, wherein the fluorine-based gas comprises a fluorocarbon gas or NF₃.

11. The method according to claim 10, wherein the fluorine-based gas for the main etching operation comprises CF₄, CHF₃, and CH₂F₂.

12. The method according to claim 10, wherein the fluorine-based gas for the over etching operation comprises CF₄, CH₃F, and CH₂F₂.

13. The method according to claim 6, wherein the oxidizing gas comprises, O₂.

14. The method according to claim 6, wherein the helium-based gas comprises a helium gas, or a mixture of a helium gas and an argon gas.

15. The method according to claim 2, wherein the main etching operation is stopped by an endpoint detection system which is triggered by a change in spectrum lines of reactants and resultants, and then the over etching operation is started, so as to etch the dielectric layer away on the entire wafer.

16. The method according to claim 2, wherein the main etching operation is performed for a time period required for the main etching to proceed to the proximity to a surface of the substrate, which is calculated based on an etching rate, and then the over etching operation is started, so as to etch the dielectric layer away on the entire wafer.

17. The method according to claim 2, wherein the main etching operation and/or the over etching operation is performed in an etcher apparatus based on a CCP or ICP mode.

18. The method according to claim 2, wherein the first dielectric layer is etched by a HF-based wet etching solution.

19. The method according to claim 1, further comprising:

implanting ions into the substrate, with the first and second spacers as a mask, to form source and drain regions;

removing the dummy gate stack to form a gate groove; and

filling a gate dielectric layer comprising a high K material and a gate conductor layer comprising a metal material into the gate groove, to form a high K-metal gate stack.