LAYERED ARCHITECTURE FOR HYBRID CONTROLLER
First Claim
1. A controller for a hybrid memory comprising a main memory and a cache for the main memory, the controller comprising a hierarchy of abstraction layers each abstraction layer configured to provide at least one component of a cache management structure, each pair of abstraction layers comprising processors communicating through an application programming interface (API), the controller configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
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Abstract
Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
121 Citations
11 Claims
- 1. A controller for a hybrid memory comprising a main memory and a cache for the main memory, the controller comprising a hierarchy of abstraction layers each abstraction layer configured to provide at least one component of a cache management structure, each pair of abstraction layers comprising processors communicating through an application programming interface (API), the controller configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
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11. A method of controlling a hybrid memory comprising a main memory and a cache for the main memory, the method comprising:
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receiving incoming memory access requests from a host processor in a first abstraction layer of a hybrid memory controller, each memory access request including a range of host logical block addresses (LBAs); implementing a first component of a cache management protocol in the first abstraction layer; routing incoming memory access requests to a second abstraction layer, the first and second abstraction layers communicating through a software interface; in the second abstraction layer, implementing a second component of the cache management protocol; mapping the range of host LBAs to cache LBAs in the second abstraction layer; and transforming the incoming memory access requests to outgoing memory access requests that include the cache LBAs; and accessing the cache using the outgoing memory access requests.
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Specification