AGGREGATION OF SEMICONDUCTOR DEVICES AND THE METHOD THEREOF

• US 20140027790A1
• Filed: 06/05/2013
• Published: 01/30/2014
• Est. Priority Date: 07/26/2012
• Status: Active Grant

• Current Assignee: Epistar Corporation
• Original Assignee: Epistar Corporation
• Inventors: LIN, Hsu-Cheng, CHIU, Ching-Yi, FANG, Pei-Shan, CHEN, Chun-Chang
• Granted Patent: US 9,006,756 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/14 including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation radiation-sensitive components structurally associated with one or more electric light sources only H01L31/14; couplings of light guides with optoelectronic elements G02B6/42
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 31/048 Encapsulation of modules
• CPC Class Codes: H01L 31/1876 Particular processes or apparatus for batch treatment of the devices
• CPC Class Codes: H01L 33/0054 for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/54 having a particular shape
• CPC Class Codes: Y02E 10/50 : Photovoltaic [PV] energy

Abstract

An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Claims

1. An aggregation of semiconductor devices, comprising:

a first layer comprising a first surface and a second surface;

a second layer comprising a first region and a second region; and

a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

2. An aggregation of semiconductor devices according to claim 1, wherein the plurality of semiconductor devices comprises a LED chip or a photovoltaic chip.

3. An aggregation of semiconductor devices according to claim 1, wherein the mark comprises a flat side.

4. An aggregation of semiconductor devices according to claim 1, further comprises a tag on a corner of the first layer.

5. An aggregation of semiconductor devices according to claim 1, wherein the shape is approximately a circle.

6. An aggregation of semiconductor devices according to claim 1, wherein the farthest straight-line distance between any two points of the shape is not greater than 15 cm.

7. An aggregation of semiconductor devices according to 1, further comprises an adhesive glue layer between the first layer and the second layer.

8. An aggregation of semiconductor devices according to 7, wherein the plurality of semiconductor devices is adhered to the adhesive glue layer.

9. An aggregation of semiconductor devices according to 7, wherein the first layer is adhered to the second layer by the adhesive glue layer.

10. An aggregation of semiconductor devices according to claim 7, wherein each of the plurality of semiconductor devices comprises a back surface and an upper surface, and the back surface is adhered to the adhesive glue layer.

11. An aggregation of semiconductor devices according to claim 10, wherein each of the plurality of semiconductor devices further comprises a conductive pad on the upper surface.

12. An aggregation of semiconductor devices according to claim 3, wherein the semiconductor devices are aligned to each other.

13. An aggregation of semiconductor devices according to claim 12, wherein a distance between adjacent two of the semiconductor devices is between 50 μ

m and 5 mm.

14. An aggregation of semiconductor devices according to claim 12, wherein the plurality of semiconductor devices is arranged as a column.

15. An aggregation of semiconductor devices according to claim 14, wherein the column is parallel to the mark.

16. An aggregation of semiconductor devices according to claim 1, wherein the material of the second layer comprises Supercalendered Kraft paper (SCK), clay coated Kraft paper (CCK), machine finished Kraft paper (MFK), machine glazed paper (MG), PVC, PE, PP, PU, PEV, or the mixture thereof.

17. An aggregation of semiconductor devices according to claim 1, wherein the first layer is capable of being expanded to over 2 times of the original area size of the first layer.

18. A method of manufacturing an aggregation of semiconductor devices comprising the steps:

providing a first layer comprising an adhesive glue layer formed thereon;

sequentially addressing and adhering a plurality of semiconductor devices to the adhesive glue layer;

providing a second layer; and

forming a second region by adhering the second layer to the first layer by the adhesive glue layer to cover the plurality of semiconductor devices,

wherein the shape of the second region comprises a curve and a mark.

19. A method of manufacturing an aggregation of semiconductor devices according to claim 18, wherein the plurality of semiconductor devices is arranged as a column.

20. A method of manufacturing an aggregation of semiconductor devices according to claim 18, wherein the plurality of the semiconductor devices is arranged as a plurality of columns so the plurality of the semiconductor devices is sequentially addressed and adhered from column to column.