DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE

• US 20140032825A1
• Filed: 10/03/2013
• Published: 01/30/2014
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 9,063,846 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.

Claims

1. A method for operating a solid state drive, comprising:

receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive; and

managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.

2. The method of claim 1, wherein managing the number of write IOPs performed by the solid state drive includes limiting the number of write IOPs performed by the solid state drive.

3. The method of claim 2, wherein managing the number of write IOPs performed by the solid state drive includes limiting the number of write IOPs performed by the solid state drive to have the solid state drive perform the desired number of write IOPs per unit time.

4. The method of claim 2, further including not limiting the number of write IOPs performed during a burst time period.

5. The method of claim 4, wherein managing the number of write IOPs performed further includes limiting the number of write IOPs at least partially based on the number of write IOPs performed during the burst time period.

6. The method of claim 1, further including sending the number of write IOPs performed by the solid state drive to a self-monitoring, analysis and reporting technology (SMART) interface of the solid state drive.

7. The method of claim 1, further including wear leveling the solid state drive at least partially based on the number of write IOPs performed by the solid state drive.

8. The method of claim 1, further including receiving an indication of the number of spare blocks in the solid state drive and the desired operational life for the solid state drive.

9. The method of claim 8, wherein receiving the indication of the desired number of write IOPs per unit time performed by the solid state drive, the number of spare blocks in the solid state drive, and the desired operational life of the solid state drive comprises receiving the indications from a user through a user interface associated with the solid state drive.

10. A method for managing wear on a solid state drive, comprising:

receiving a number of spare blocks in a solid state drive;

receiving a desired operational life for the solid state drive; and

managing program and/or erase cycles on the solid state drive at least partially based on the number of spare blocks and the desired operational life.

11. The method of claim 10, wherein managing further includes allowing a limited number of program and/or erase cycles.

12. The method of claim 10, further including not limiting the number of program and/or erase cycles over a burst time period.

13. The method of claim 12, further includes receiving an allowable burst time period from an interface.

14. The method of claim 12, wherein the method includes recalculating via a feedback loop an allowable program and/or erase cycles rate at least partially based on the number of program and/or erase cycles performed during the burst time period.

15. The method of claim 12, wherein the method includes monitoring the number of program and/or erase cycles performed over a particular time period to determine how to calculate the allowable program and/or erase cycle rate.

16. A solid state memory device, comprising:

a number of solid state memory arrays; and

a controller coupled to the solid state memory arrays and configured to;

receive a number of spare blocks in the solid state memory arrays,

receive a desired operational life for the solid state memory arrays, and

manage a number of write input/outputs operations (IOPs) performed by the solid state memory arrays.

17. The solid state memory device of claim 16, wherein the controller manages the write IOPs rate of the solid state memory arrays based, at least partially, upon the number of space blocks in the solid state drive and the desired operational life for the solid state memory arrays.

18. The solid state memory device of claim 16, wherein the controller dynamically manages host traffic on the solid state device to reduce wear of the number of solid state memory arrays.

19. The solid state memory device of claim 18, wherein the controller dynamically manages host traffic on the solid state device by acknowledging write IOPs requests with increased delay.

20. The solid state memory device of claim 16, wherein the control circuitry includes a wear leveling operation that is at least partially based on the number of write IOPs performed by the solid state drive.