UNDISCOVERABLE PHYSICAL CHIP IDENTIFICATION

• US 20140033330A1
• Filed: 07/30/2012
• Published: 01/30/2014
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kothandaraman, Chandrasekharan, Fainstein, Daniel Jacob
• Granted Patent: US 8,950,008 B2
• Time in Patent Office: Days
• US Class Current: 726/30
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 21/30 Authentication, i.e. establishing the identity or authorisation of security principals
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H02H 3/24 responsive to undervoltage or no-voltage H02H3/207 takes precedence
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

Claims

1. An electronic circuit comprising:

a first transistor having a first threshold voltage variability;

a second transistor having a second threshold voltage variability;

wherein;

the first transistor comprises a first endpoint node connected to a first voltage and a second endpoint node connected to a second voltage;

the second transistor comprises a first endpoint node connected to the first voltage and a second endpoint node connected to the second voltage;

an enable signal configured and disposed to control a gate of the first transistor and a gate of the second transistor; and

a difference detection circuit disposed between the first endpoint node of the first transistor and the first endpoint node of the second transistor, wherein the difference detection circuit is configured and disposed to generate a signal indicative of a difference in threshold voltage between the first transistor and the second transistor.

2. The circuit of claim 1, wherein the difference detection circuit comprises a cross-coupled inverter circuit.

3. The circuit of claim 1, wherein the difference detection circuit comprises a comparator circuit.

4. The circuit of claim 1, wherein the first transistor has a channel width that is smaller than a channel width of the second transistor and wherein the first transistor has a channel length that is smaller than a channel length of the second transistor;

and wherein a ratio of channel width to channel length of the first transistor is substantially equal to a ratio of channel width to channel length of the second transistor.

5. The circuit of claim 2, further comprising:

a first capacitor disposed between the first endpoint node of the first transistor and the second endpoint node of the first transistor; and

a second capacitor disposed between the first endpoint node of the second transistor and the second endpoint node of the second transistor.

6. The circuit of claim 1, wherein the first transistor has a threshold voltage standard deviation value that ranges from three to four times a threshold voltage standard deviation value of the second transistor.

7. An integrated circuit comprising:

a plurality of intrinsic bit elements, wherein each intrinsic bit element of the plurality of intrinsic bit elements comprises;

a first transistor having a first threshold voltage variability;

a second transistor having a second threshold voltage variability;

wherein;

the first transistor comprises a first endpoint node connected to a first voltage and a second endpoint node connected to a second voltage;

the second transistor comprises a first endpoint node connected to the first voltage and a second endpoint node connected to the second voltage;

an enable signal configured and disposed to control a gate of the first transistor and a gate of the second transistor; and

a difference detection circuit disposed between the first endpoint node of the first transistor and the first endpoint node of the second transistor, wherein the difference detection circuit is configured and disposed to generate a signal indicative of a difference in threshold voltage between the first transistor and the second transistor.

8. The integrated circuit of claim 7, wherein the difference detection circuit of each intrinsic bit element comprises a cross-coupled inverter circuit.

9. The integrated circuit of claim 7, wherein the difference detection circuit of each intrinsic bit element comprises a comparator circuit.

10. The integrated circuit of claim 7, wherein for each intrinsic bit element;

the first transistor has a channel width that is smaller than a channel width of the second transistor and the first transistor has a channel length that is smaller than a channel length of the second transistor; and

a ratio of channel width to channel length of the first transistor is substantially equal to a ratio of channel width to channel length of the second transistor.

11. The integrated circuit of claim 8, wherein each intrinsic bit element further comprises a first capacitor disposed between the first endpoint node of the first transistor and the second endpoint node of the first transistor;

and

a second capacitor disposed between the first endpoint node of the second transistor and the second endpoint node of the second transistor.

12. The integrated circuit of claim 7, wherein for each intrinsic bit element, the first transistor has a threshold voltage standard deviation value that ranges from three to four times a threshold voltage standard deviation value of the second transistor.

13. The integrated circuit of claim 7, comprising a plurality of banks of intrinsic bit elements, wherein each bank of intrinsic bit elements is configured and disposed to generate a data string.

14. The integrated circuit of claim 13, wherein the plurality of banks of intrinsic bit elements comprises four banks, and wherein each bank comprises at least 64 intrinsic bit elements.

15. A method of generating a unique number within a chip comprising:

configuring a plurality of intrinsic bit elements within a chip, wherein each intrinsic bit element is configured to generate a bit value; and

generating a data value string comprised of data from the plurality of intrinsic bit elements.

16. The method of claim 15, further comprising comparing the generated data value string with a previously stored related value, and, indicating a successful authentication in response to a match between the generated data value string and the previously stored related value.

17. The method of claim 15, further comprising identifying one or more don'"'"'t-care bits within the plurality of intrinsic bit elements.

18. The method of claim 17, wherein identifying one or more don'"'"'t-care bits comprises:

reading the data value string at a plurality of different VDD voltage values;

identifying bits that flip during the reading; and

designating the bits that flip during the reading as don'"'"'t-care bits.

19. The method of claim 18, further comprising:

classifying a the chip as failed if the number of bits designated as don'"'"'t-care bits exceeds a predetermined limit.

20. The method of claim 15, further comprising:

generating a plurality of data value strings from a plurality of banks of intrinsic bit elements; and

comparing each of the plurality of data value strings with a corresponding previously stored related value; and

indicating a successful authentication in response to a match between a subset of the plurality of data value strings and the corresponding previously stored related value.