DISPLAY PANEL, THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME

• US 20140034944A1
• Filed: 03/15/2013
• Published: 02/06/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: E Ink Holdings Incorporated
• Original Assignee: E Ink Holdings Incorporated
• Inventors: Zan, Hsiao-Wen, Tsai, Chuang-Chuang, Tsai, Xue-Hung, Wang, Henry, Chen, Wei-Tsung
• Granted Patent: US 9,368,634 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.

Claims

1. A method of fabricating a thin film transistor, comprising:

providing a first base;

forming a gate on the first base;

forming a dielectric layer on the first base;

forming a metal-oxide semiconductor channel on the first base, the metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and

forming a source and a drain on the first base, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel.

2. The method as recited in claim 1, wherein the nano micro structures are a plurality of nano particles.

3. The method as recited in claim 2, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:

placing the nano particles on the first base; and

forming the metal-oxide semiconductor layer on the nano particles to cover the nano particles.

4. The method as recited in claim 2, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:

providing the nano particles;

providing a metal-oxide semiconductor precursor;

mixing the nano particles and the metal-oxide semiconductor precursor to form a mixed solution; and

solidifying the mixed solution on the first base to form the metal-oxide semiconductor channel.

5. The method as recited in claim 2, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.

6. The method as recited in claim 1, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.

7. The method as recited in claim 6, wherein the step of forming the metal-oxide semiconductor channel on the first base comprises:

forming a metal-oxide semiconductor pre-channel on the first base, the metal-oxide semiconductor pre-channel comprising the metal-oxide semiconductor layer and the nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another;

removing the nano particles in the metal-oxide semiconductor layer to form the nano pores; and

performing surface treatment on the inner walls of the nano pores to effect conductivity of the inner walls of the nano pores.

8. The method as recited in claim 7, wherein the step of removing the nano particles in the metal-oxide semiconductor layer comprises:

removing the nano particles in the metal-oxide semiconductor layer by means of an adhesive, a solvent, or plasma.

9. The method as recited in claim 7, wherein the step of performing the surface treatment on the inner walls of the nano pores to effect the conductivity of the inner walls of the nano pores comprises:

performing the surface treatment on the inner walls of the nano pores by means of plasma, a reactive gas, ultraviolet light, or a reactive liquid.

10. The method as recited in claim 7, wherein a material of the nano particles is organic.

11. A thin film transistor comprising:

a gate;

a dielectric layer;

a metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and

a source and a drain, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel.

12. The thin film transistor as recited in claim 11, wherein the nano micro structures are a plurality of nano particles.

13. The thin film transistor as recited in claim 12, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.

14. The thin film transistor as recited in claim 11, wherein a material of the metal-oxide semiconductor layer comprises aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium gallium oxide (IGO), zinc oxide (ZnO), cadmium oxide•

germanium dioxide (2CdO•

GeO₂), or nickel cobalt oxide (NiCo₂O₄), and a material of the nano micro structures comprises ITO or IZO.

15. The thin film transistor as recited in claim 11, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.

16. A display panel comprising:

a thin film transistor array substrate comprising;

a first base; and

a plurality of thin film transistors arranged in arrays on the first base, each of the thin film transistors comprising;

a gate;

a dielectric layer;

a metal-oxide semiconductor channel comprising a metal-oxide semiconductor layer and a plurality of nano micro structures, the nano micro structures being located in the metal-oxide semiconductor layer and separated from one another; and

a source and a drain, wherein the gate and the metal-oxide semiconductor channel are overlapped, the gate, the source, and the drain are separated by the dielectric layer, and the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel;

an opposite substrate disposed opposite to the thin film transistor array substrate; and

a display medium disposed between the thin film transistor array substrate and the opposite substrate.

17. The display panel as recited in claim 16, wherein the nano micro structures are a plurality of nano particles.

18. The display panel as recited in claim 17, wherein carrier concentration of the nano particles is greater than carrier concentration of the metal-oxide semiconductor layer.

19. The display panel as recited in claim 16, wherein a material of the metal-oxide semiconductor layer comprises aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium-gallium-zinc oxide (IGZO), indium gallium oxide (IGO), zinc oxide (ZnO), cadmium oxide•

germanium dioxide (2CdO•

GeO₂), or nickel cobalt oxide (NiCo₂O₄), and a material of the nano micro structures comprises ITO or IZO.

20. The display panel as recited in claim 16, wherein each of the nano micro structures is a nano pore, and inner walls of the nano pores are conductive.