VOLTAGE REGULATOR CIRCUIT

• US 20140035550A1
• Filed: 08/03/2012
• Published: 02/06/2014
• Est. Priority Date: 08/03/2012
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: CHEN, Shi-Wen
• Granted Patent: US 8,970,197 B2
• Time in Patent Office: Days
• US Class Current: 323/311
• CPC Class Codes: G05F 1/618 using semiconductor devices in series and in parallel with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/08 wherein the variable is dc

Abstract

A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage.

Claims

1. A voltage regulator circuit, comprising:

a plurality of first transistors, each first transistor having a first source/drain terminal, a second source/drain terminal and a first gate terminal, the first source/drain terminal being electrically coupled to a source voltage, the second source/drain terminal being electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit; and

a control circuit electrically coupled to the first gate terminals and configured to determine the number of the first transistors to be turned on according to the difference between the voltage at the output terminal and a first predetermined reference voltage.

2. The voltage regulator circuit according to claim 1, wherein the control circuit comprises:

a plurality of sense amplifiers, each sense amplifier being electrically coupled to one of the first gate terminals and configured to compare the voltage at the output terminal with one of a plurality of second predetermined reference voltages, so as to generate a comparison result to turn on or turn off a corresponding first transistor according to the comparison result, wherein the second predetermined reference voltages are smaller than the first predetermined reference voltage, and the second predetermined reference voltages are obtained through multiplying the first predetermined reference voltage by a plurality of respective different predetermined percentages.

3. The voltage regulator circuit according to claim 1, wherein the control circuit comprises:

a first phase delay unit, comprising;

a first delay chain comprising a plurality of first internal circuits coupled in series and configured to receive a clock signal and delay the phase of the received clock signal; and

a plurality of first delay control units, each first delay control unit being configured to control the time delay degree of a signal received by a corresponding first internal circuit according to the value of the voltage at the output terminal of the voltage regulator circuit;

a second phase delay unit, comprising;

a second delay chain comprising a plurality of second internal circuits coupled in series and configured to receive the clock signal and delay the phase of the received clock signal; and

a plurality of second delay control units, each second delay control unit being configured to control the time delay degree of a signal received by a corresponding second internal circuit according to the value of the first predetermined reference voltage; and

a plurality of phase comparison units, each phase comparison unit being electrically coupled to an output of a corresponding stage of the first internal circuits in the first delay chain and an output of a corresponding stage of the second internal circuits in the second delay chain and configured to compare the phases of the two output signals, so as to generate a comparison result and turn on or turn off a corresponding first transistor based on the comparison result.

4. The voltage regulator circuit according to claim 3, wherein each of the first internal circuits and the second internal circuits comprises an inverter, each of the first delay control units and the second delay control units comprises a transistor, each transistor in the first delay control units is configured to have its gate terminal receiving the voltage at the output terminal of the voltage regulator circuit, each transistor in the second delay control unit is configured to have its gate terminal receiving the first predetermined reference voltage, each inverter is electrically coupled to ground via one corresponding transistor either in the first delay control unit or in the second delay control unit.

5. The voltage regulator circuit according to claim 3, wherein each phase comparison unit comprises a D-type flip-flop having a signal input terminal, a clock input terminal and a signal output terminal, the signal and clock input terminals are configured to receive the output signals of two corresponding stages of the internal circuits in the first and second delay chains, respectively, and the signal output terminal is configured to output one of the comparison results.

6. The voltage regulator circuit according to claim 1, wherein the first transistors have the same element size.

7. The voltage regulator circuit according to claim 1, wherein the first transistors have different element sizes.

8. The voltage regulator circuit according to claim 1, further comprising:

a plurality of second transistors, each second transistor having a third source/drain, a fourth source/drain terminal and a second gate terminal, the third source/drain terminal being electrically coupled to the output terminal of the voltage regulator circuit, the fourth source/drain terminal being electrically coupled to a reference voltage,

wherein the control circuit is further electrically coupled to the second gate terminals and configured to determine the number of the second transistors to be turned on according to the difference between the voltage at the output terminal and the first predetermined reference voltage.

9. The voltage regulator circuit according to claim 8, wherein the control circuit comprises:

a plurality of first sense amplifiers, each first sense amplifier being electrically coupled to a corresponding first gate terminal and configured to compare the voltage at the output terminal with one of a plurality of second predetermined reference voltages, so as to generate a first comparison result and turn on or turn off a corresponding first transistor according to the first comparison result, wherein the second predetermined reference voltages are smaller than the first predetermined reference voltage, and the second predetermined reference voltages are obtained through multiplying the first predetermined reference voltage by a plurality of different predetermined percentages; and

a plurality of second sense amplifiers, each second sense amplifier being electrically coupled to a corresponding second gate terminal and configured to compare the voltage at the output terminal with one of a plurality of third predetermined reference voltages, so as to generate a second comparison result and turn on or turn off a corresponding second transistor according to the second comparison result, wherein the third predetermined reference voltages are greater than the first predetermined reference voltage, and the third predetermined reference voltages are obtained through multiplying the first predetermined reference voltage by a plurality of different predetermined percentages.

10. The voltage regulator circuit according to claim 8, wherein the control circuit comprises:

a first phase delay unit, comprising;

a first delay chain comprising a plurality of first internal circuits coupled in series and configured to receive a clock signal and delay the phase of the received clock signal; and

a plurality of first delay control units, each first delay control unit being configured to control the time delay degree of a signal received by a corresponding first internal circuit according to the value of the voltage at the output terminal of the voltage regulator circuit;

a second phase delay unit, comprising;

a second delay chain comprising a plurality of second internal circuits coupled in series and configured to receive the clock signal and delay the phase of the received clock signal; and

a plurality of second delay control units, each second delay control unit being configured to control the time delay degree of a signal received by a corresponding second internal circuit according to the value of the first predetermined reference voltage;

a plurality of first phase comparison units, each first phase comparison unit being electrically coupled to an output of a corresponding stage of the first internal circuits in the first delay chain and an output of a corresponding stage of the second internal circuits in the second delay chain and configured to compare the phases of the two output signals, so as to generate a first comparison result and turn on or turn off a corresponding first transistor based on the first comparison result;

a third phase delay unit, comprising;

a third delay chain comprising a plurality of third internal circuits coupled in series and configured to receive an inversion signal of the clock signal and delay the phase of the received inversion signal of the clock signal; and

a plurality of third delay control units, each third delay control unit being configured to control the time delay degree of a signal received by a corresponding third internal circuit according to the value of the first predetermined reference voltage;

a fourth phase delay unit, comprising;

a fourth delay chain comprising a plurality of fourth internal circuits coupled in series and configured to receive the inversion signal of the clock signal and delay the phase of the received inversion signal of the clock signal; and

a plurality of fourth delay control units, each fourth delay control unit being configured to control the time delay degree of a signal received by a corresponding fourth internal circuit according to the value of the voltage at the output terminal of the voltage regulator circuit; and

a plurality of second phase comparison units, each second phase comparison unit being electrically coupled to an output of a corresponding stage of the third internal circuits in the third delay chain and an output of a corresponding stage of the fourth internal circuits in the fourth delay chain and configured to compare the phases of the two output signals, so as to generate a second comparison result and turn on or turn off a corresponding second transistor based on the second comparison result.

11. The voltage regulator circuit according to claim 10, wherein each of the first, second, third and fourth internal circuits comprises an inverter, each of the first, second, third and fourth delay control units comprises a transistor, each transistor in the first and fourth delay control units is configured to have its gate terminal receiving the voltage at the output terminal of the voltage regulator circuit, each transistor in the second and third delay control units is configured to have its gate terminal receiving the first predetermined reference voltage, each inverter is electrically coupled to the reference voltage via one corresponding transistor in one of the first, second, third and fourth delay control units.

12. The voltage regulator circuit according to claim 10, wherein each of the first phase comparison units and the second phase comparison comprises a D-type flip-flop having a signal input terminal, a clock input terminal and a signal output terminal, the signal and clock input terminals are configured to receive the output signals of two corresponding stages of the internal circuits in the first and second delay chains respectively or receive the output signals of two corresponding stages of the internal circuits in the third and fourth delay chains respectively, and the signal output terminal is configured to output one of the first comparison results or one of the second comparison results.

13. The voltage regulator circuit according to claim 8, wherein the first and second transistors have the same element size.

14. The voltage regulator circuit according to claim 8, wherein the first transistors and the second transistors have different element sizes.