Sense Amplifier for Flash Memory

• US 20140036596A1
• Filed: 07/31/2012
• Published: 02/06/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chan, Johnny, Huang, Koying
• Granted Patent: US 8,953,384 B2
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.

Claims

1. A sense amplifier for sensing data stored in a selected memory cell of a flash memory array, comprising:

a differential amplifier;

a reference cell current branch comprising a reference cell, a first drain bias section coupled to the reference cell, and a first load section coupled to the first drain bias section and to a first input of the differential amplifier;

a main cell current branch comprising a selected memory cell, a second drain bias section coupled to the selected memory cell, and a second load section coupled to the second drain bias section and to a second input of the differential amplifier; and

a boost circuit comprising a pull-up section coupled to the second input of the differential amplifier and a pull-down section coupled to the selected memory cell.

2. The sense amplifier of claim 1 further comprising:

a boost activation signal node; and

a bias voltage node;

wherein the pull up section of the boost circuit comprises a MOSFET pull-up transistor having a gate coupled to the boost activation signal node; and

wherein the pull down section of the boost circuit comprises a MOSFET pull-down transistor having a gate coupled to the bias voltage node.

3. The sense amplifier of claim 2 wherein:

the second load section comprises a MOSFET load transistor having a predetermined pull-up strength;

the MOSFET pull-up transistor has a pull-up strength greater than the pull-up strength of the MOSFET load transistor; and

the MOSFET pull-down transistor has a pull-down strength to substantially compensate for any change in the DC voltage level in the main cell current branch from the MOSFET pull-up transistor.

4. The sense amplifier of claim 3 wherein:

the pull-up strength of the MOSFET pull-up transistor is twice the pull-up strength of the MOSFET load transistor; and

the pull-down strength of the MOSFET pull-down transistor is twice the pull-down strength of a memory cell in a logical one state.

5. The sense amplifier of claim 1 further comprising:

a boost activation signal node coupled to the pull-up section of the boost circuit; and

a bias voltage node coupled to the pull-down section of the boost circuit.

6. A method of operating a sense amplifier for reading data stored in a selected memory cell of a flash memory array, comprising:

activating a reference cell current branch comprising a reference cell, a first drain bias section coupled to the reference cell, and a first load section coupled to the first drain bias section and to a first input of the differential amplifier, wherein a reference voltage is established across the first load section;

activating a main cell current branch comprising a selected memory cell, a second drain bias section coupled to the selected memory cell, and a second load section coupled to the second drain bias section and to a second input of the differential amplifier, wherein a sense voltage dependent on the data stored in the selected memory cell is established across the second load section;

activating a boost circuit comprising a pull-up section coupled to the second input of the differential amplifier and a pull-down section coupled to the selected memory cell;

applying the reference voltage to a first input of a differential amplifier, and the sense voltage to a second input of the differential amplifier; and

providing a digital output level from the differential amplifier in accordance with a difference between the reference voltage on the first input of the differential amplifier, and the sense voltage on the first input of the differential amplifier.

7. The method of claim 6 wherein the reference cell current branch activating step precedes the main cell current branch activating step, and wherein the main cell current branch activating step and the boost circuit activating step occur substantially simultaneously.

8. The method of claim 6 wherein the boost circuit establishes a predetermined zero sensing time, further comprising deactivating the boost circuit substantially at the predetermined zero sensing time:

9. A sense amplifier for sensing data stored in a selected memory cell of a flash memory array, comprising:

a differential amplifier;

a V_CC voltage node;

a V_SS voltage node;

a reference cell current branch activation signal node;

a first cell select NMOS transistor;

a second cell select NMOS transistor;

a reference cell floating gate MOSFET transistor;

a first PMOS transistor switch having a source coupled to the V_cc voltage node, a gate coupled to the reference cell current branch activation signal node, and a drain;

a first NMOS transistor load having a drain coupled to the drain of the first PMOS switching transistor, a source coupled to a plus input of the differential amplifier, and a gate coupled to the V_CC voltage node;

a first NMOS transistor variable conductor having a drain coupled to the source of the first NMOS transistor load, a source coupled to the reference cell floating gate MOSFET transistor through the first and second cell select NMOS transistors, and a gate;

a first NMOS transistor feedback element having a drain coupled to the gate of the first NMOS transistor variable conductor, a source coupled to the V_SS voltage node, and a gate coupled to the source of the first NMOS transistor variable conductor;

a second PMOS transistor switch having a source coupled to the V_CC voltage node, a gate coupled to the reference cell activation signal node, and a drain;

a first PMOS transistor load having a source coupled to the drain of the first PMOS switching transistor, a drain coupled to the drain of the first NMOS transistor feedback element, and a gate coupled to the drain of the first PMOS transistor load;

a main cell current branch activation signal node;

a third cell select NMOS transistor;

a fourth cell select NMOS transistor;

a main cell floating gate MOSFET transistor selected from an array of floating gate MOSFET transistors by the third and fourth cell select NMOS transistors;

a third PMOS transistor switch having a source coupled to the V_CC voltage node, a gate coupled to the main cell current branch activation signal node, and a drain;

a second NMOS transistor load having a drain coupled to the drain of the second PMOS switching transistor, a source coupled to a minus input of the differential amplifier, and a gate coupled to the V_CC voltage node;

a second NMOS transistor variable conductor having a drain coupled to the source of the second NMOS transistor load, a source coupled to the main cell floating gate MOSFET transistor through the third and fourth cell select NMOS transistors, and a gate;

a second NMOS transistor feedback element having a drain coupled to the gate of the second NMOS transistor variable conductor, a source coupled to the V_SS voltage node, and a gate coupled to the source of the second NMOS transistor variable conductor;

a fourth PMOS transistor switch having a source coupled to the V_CC voltage node, a gate coupled to the main cell current branch activation signal node, and a drain;

a second PMOS transistor load having a source coupled to the drain of the second PMOS switching transistor, a drain coupled to the drain of the second NMOS transistor feedback element, and a gate coupled to the drain of the second PMOS transistor load;

a boost circuit activation signal node;

a fifth PMOS transistor switch having a source coupled to the V_CC voltage node, a gate coupled to the boost circuit activation signal node, and a drain;

a NMOS pull up transistor having a drain coupled to the drain of the fifth PMOS transistor switch, a source coupled to the source of the second NMOS transistor load, and a gate coupled to the V_CC voltage node;

a boost circuit bias voltage node; and

a NMOS pull down transistor having a source coupled to the V_SS voltage node, a drain coupled to the source of the second NMOS transistor load, and a gate coupled to the boost circuit bias voltage node.