MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
First Claim
1. A method performed by logic circuitry disposed on a card having a connector to plug into a memory channel that supports near memory cache accesses and far memory accesses, comprising:
- receiving from said memory channel a first tag component of a target address of a read request transaction being processed by a host that is coupled to said memory channel;
receiving a second tag component of an address of a cache line read from a near memory cache in response to said read request transaction; and
,comparing said first and second tag components to determine if said cache line corresponds to a cache hit or a cache miss.
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Accused Products
Abstract
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
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Citations
25 Claims
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1. A method performed by logic circuitry disposed on a card having a connector to plug into a memory channel that supports near memory cache accesses and far memory accesses, comprising:
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receiving from said memory channel a first tag component of a target address of a read request transaction being processed by a host that is coupled to said memory channel; receiving a second tag component of an address of a cache line read from a near memory cache in response to said read request transaction; and
,comparing said first and second tag components to determine if said cache line corresponds to a cache hit or a cache miss. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor chip, comprising:
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an interface to a memory channel; a read buffer to hold a far memory read request received from said memory channel; logic circuitry to detect a cache miss of a cache line read from a near memory in response to a near memory read request issued on said memory channel, said near memory a cache for said far memory, said logic circuitry to additionally perform at least one of the following in response thereto; initiate a read of a desired cache line from said far memory, said desired cache line containing data sought by a transaction that caused said near memory read request to be issued on said memory channel; detect that a dirty bit of said cache line read from near memory is set and automatically writing said cache line read from said near memory into far memory. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor chip comprising:
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memory controller circuitry having interface circuitry to couple to a memory channel, the memory controller circuitry including; first logic circuitry to implement a first memory channel protocol on the memory channel through the interface circuitry, said first memory channel protocol specific to a first volatile system memory technology; second logic circuitry to implement a second memory channel protocol on the memory channel through the interface circuitry, said second memory channel protocol specific to a second non volatile system memory technology, said second memory channel protocol being a transactional protocol. - View Dependent Claims (18, 19, 20)
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21. A computer system, comprising:
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memory controller circuitry having interface circuitry to couple to a memory channel, the memory controller circuitry including; first logic circuitry to implement a first memory channel protocol on the memory channel through the interface circuitry, said first memory channel protocol specific to a first volatile system memory technology; second logic circuitry to implement a second memory channel protocol on the memory channel through the interface circuitry, said second memory channel protocol specific to a second non volatile system memory technology, said second memory channel protocol being a transactional protocol; a first memory device composed of the first volatile system memory technology coupled to the memory channel; and
,a second memory device composed of the second non volatile system memory technology coupled to the memory channel. - View Dependent Claims (22, 23, 24)
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25. The computer system 24 wherein said far memory control circuitry is also between said channel and said first memory device along said command bus.
Specification