MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION

• US 20140040568A1
• Filed: 08/20/2013
• Published: 02/06/2014
• Est. Priority Date: 07/16/2009
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Bhakta, Jayesh R.
• Granted Patent: US 9,606,907 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory module is operable to communicate with a memory controller via a data bus and a control/address bus and comprises a module board; a plurality of memory devices mounted on the module board; and multiple sets of data pins along an edge of the module board. Each respective set of the multiple sets of data pins is operatively coupled to a respective set of multiple sets of data lines in the data bus. The memory module further comprises a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals. The memory module further comprises a plurality of buffer circuits each being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins. Each buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

Claims

1. A memory module to communicate with a memory controller via a data bus and a control/address bus, the data bus comprising multiple sets of data lines, comprising:

a module board;

a plurality of memory devices mounted on the module board;

multiple sets of data pins along an edge of the module board, each respective set of the multiple sets of data pins being operatively coupled a respective set of the multiple sets of data lines;

a control circuit configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals; and

a plurality of buffer circuits, each respective buffer circuit being disposed proximate to and electrically coupled to a respective set of the multiple sets of data pins, the respective buffer circuit is configured to respond to the module control signals by enabling data communication between the memory controller and at least one first memory device among the plurality of memory devices and by isolating at least one second memory device among the plurality of memory devices from the memory controller.

2. A chipset for mounting on a memory module operable to communicate with a memory controller via a data bus and a control/address bus, the memory module comprising a plurality of memory devices, the data bus comprising multiple sets of data lines, the chipset comprising:

a control circuit chip configured to receive control/address information from the memory controller via the control/address bus and to produce module control signals; and

a plurality of buffer chips, each respective buffer chip for coupling to a respective set of the multiple sets of data lines and comprising multiple data paths, the respective buffer chip is configured to respond to the module control signals by enabling a subset of the multiple data paths such that data is communicated between the memory controller and at least one first memory device among the plurality of memory devices while memory device load from at least one second memory device among the plurality memory devices is isolated from the memory controller.

3. A method of operating a memory module to communicate with a memory controller via a data bus and a control/address bus, the memory module comprising memory devices, the data bus comprising multiple sets of data lines, the method comprising:

receiving control/address information from the memory controller via the control/address bus;

generating module control signals in response to the control/address information;

transmitting the module control signals to a plurality of buffer circuits distributed across the memory module, each respective buffer circuit being coupled to a respective set of the multiple sets of data lines;

enabling data communication via the respective buffer circuit between the memory controller and at least one first memory device among the plurality of memory devices in response to the module control signals; and

isolating at least one second memory device among the plurality of memory devices from the memory controller in response to the module control signals such that the at least one second memory device does not present a load on the respective set of the multiple sets of data lines in addition to a load presented by the at least one first memory device.