SYNTHESIZING INTERMEDIATE PERFORMANCE LEVELS IN INTEGRATED CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA

• US 20140040647A1
• Filed: 01/02/2013
• Published: 02/06/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Bridges, Jeffrey Todd, Kolla, Yeshwant Nagaraj, Patel, Sanjay B.
• Granted Patent: US 9,223,384 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.

Claims

1. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit configured to:

receive as input a performance mode input; and

responsive to receiving the performance mode input indicating a synthesized performance mode;

generate a power source selection output to select a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and

generate the power source selection output to select a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and generate the clock frequency setting output to select a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval.

2. The synthesized performance level setting circuit of claim 1, further configured to:

receive as input a high performance mode timer value and a low performance mode timer value;

responsive to receiving the high performance mode timer value and the low performance mode timer value;

generate a first countdown timer initiation output initiating a countdown timer for the first predefined time interval based on the high performance mode timer value; and

generate a second countdown timer initiation output initiating the countdown timer for the second predefined time interval based on the low performance mode timer value.

3. The synthesized performance level setting circuit of claim 1 further configured to:

responsive to receiving the performance mode input indicating a high performance mode;

generate the power source selection output to select the first power source to provide power to the functional block at the first voltage level, and generate the clock frequency setting output to select the first clock frequency associated with the first voltage level to clock the functional block.

4. The synthesized performance level setting circuit of claim 1 further configured to:

responsive to receiving the performance mode input indicating a low performance mode;

generate the power source selection output to select the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and generate the clock frequency setting output to select the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.

5. The synthesized performance level setting circuit of claim 1 further configured to:

receive as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode;

responsive to receiving the performance mode override input;

generate the power source selection output to select the first power source to provide power to the functional block at the first voltage level, and generate the clock frequency setting output to select the first clock frequency associated with the first voltage level to clock the functional block.

6. The synthesized performance level setting circuit of claim 1 further configured to:

receive as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode;

responsive to receiving the performance mode override input;

generate the power source selection output to select the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and generate the clock frequency setting output to select the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.

7. The synthesized performance level setting circuit of claim 1 configured to generate the power source selection output to select a shared high voltage rail coupled to a high voltage source outside the integrated circuit as the first power source.

8. The synthesized performance level setting circuit of claim 1 configured to generate the power source selection output to select a shared high voltage rail coupled to a high voltage source outside the integrated circuit as the second power source.

9. The synthesized performance level setting circuit of claim 1 configured to generate the power source selection output to select an on-die voltage regulator integrated on a same die as the integrated circuit as the second power source.

10. The synthesized performance level setting circuit of claim 5 configured to receive as input the performance mode override input triggered by a high processor utilization condition.

11. The synthesized performance level setting circuit of claim 6 configured to receive as input the performance mode override input triggered by the predefined condition selected from the group consisting of an execution pipeline stall condition, an outstanding memory access condition, and a low processor utilization condition.

12. The synthesized performance level setting circuit of claim 1 integrated into a semiconductor die.

13. The synthesized performance level setting circuit of claim 1, further comprising a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.

14. A synthesized performance level setting circuit configured to synthesize an intermediate performance level for a functional block of an integrated circuit, the synthesized performance level setting circuit comprising:

a means for receiving as input a performance mode input;

a means for determining that the performance mode input indicates a synthesized performance mode;

a means for selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval, responsive to a determination that the performance mode input indicates the synthesized performance mode; and

a means for selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval, responsive to the determination that the performance mode input indicates the synthesized performance mode.

15. A method for synthesizing an intermediate performance level for a functional block of an integrated circuit, comprising:

receiving as input a performance mode input; and

responsive to receiving the performance mode input indicating a synthesized performance mode;

selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and

selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval.

16. The method of claim 15, further comprising:

receiving as input a high performance mode timer value and a low performance mode timer value;

initiating a countdown timer for the first predefined time interval based on the high performance mode timer value after selecting the first power source and selecting the first clock frequency; and

initiating the countdown timer for the second predefined time interval based on the low performance mode timer value after selecting the second power source and selecting the second clock frequency.

17. The method of claim 15 further comprising:

responsive to receiving the performance mode input indicating a high performance mode;

selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block.

18. The method of claim 15 further comprising:

responsive to receiving the performance mode input indicating a low performance mode;

selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.

19. The method of claim 15 further comprising:

receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode;

responsive to receiving the performance mode override input;

selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block.

20. The method of claim 15 further comprising:

receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode;

responsive to receiving the performance mode override input;

selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.

21. A non-transitory computer-readable medium having stored thereon computer-executable instructions to cause a processor to implement a method for synthesizing an intermediate performance level for a functional block of an integrated circuit, the method comprising:

receiving as input a performance mode input; and

responsive to receiving the performance mode input indicating a synthesized performance mode;

selecting a first power source to provide power to the functional block at a first voltage level for a first predefined time interval, and selecting a first clock frequency associated with the first voltage level to clock the functional block for the first predefined time interval; and

selecting a second power source to provide power to the functional block at a second voltage level lower than the first voltage level for a second predefined time interval, and selecting a second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block for the second predefined time interval.

22. The non-transitory computer-readable medium of claim 21 having stored thereon the computer-executable instructions to cause the processor to implement the method further comprising:

receiving as input a high performance mode timer value and a low performance mode timer value;

initiating a countdown timer for the first predefined time interval based on the high performance mode timer value after selecting the first power source and selecting the first clock frequency; and

initiating the countdown timer for the second predefined time interval based on the low performance mode timer value after selecting the second power source and selecting the second clock frequency.

23. The non-transitory computer-readable medium of claim 21 having stored thereon the computer-executable instructions to cause the processor to implement the method further comprising:

responsive to receiving the performance mode input indicating a high performance mode;

selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block.

24. The non-transitory computer-readable medium of claim 21 having stored thereon the computer-executable instructions to cause the processor to implement the method further comprising:

responsive to receiving the performance mode input indicating a low performance mode;

selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.

25. The non-transitory computer-readable medium of claim 21 having stored thereon the computer-executable instructions to cause the processor to implement the method further comprising:

receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a high performance mode;

responsive to receiving the performance mode override input;

selecting the first power source to provide power to the functional block at the first voltage level, and selecting the first clock frequency associated with the first voltage level to clock the functional block.

26. The non-transitory computer-readable medium of claim 21 having stored thereon the computer-executable instructions to cause the processor to implement the method further comprising:

receiving as input a performance mode override input triggered by a predefined condition within the integrated circuit and indicating a low performance mode;

responsive to receiving the performance mode override input;

selecting the second power source to provide power to the functional block at the second voltage level lower than the first voltage level, and selecting the second clock frequency lower than the first clock frequency and associated with the second voltage level to clock the functional block.