METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE

• US 20140048927A1
• Filed: 08/17/2012
• Published: 02/20/2014
• Est. Priority Date: 08/17/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Burke, Chad M., Li, Baozhen, Wong, Keith Kwong Hon, Yang, Chih-Chao
• Granted Patent: US 9,224,640 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.

Claims

1. A semiconductor structure, comprising:

a plurality of layers comprising at least one copper interconnect layer, said copper interconnect layer providing an electrical conduit between at least one of;

physically adjacent layers in said semiconductor structure, and

an integrated circuit in said semiconductor structure and an electronic device; and

a plurality of studs positioned within said at least one copper interconnect layer, said studs being spaced apart by a distance less than or equal to a Blech length of said at least one copper interconnect layer,

said Blech length comprising a length below which damage due to electromigration of metal atoms within said at least one copper interconnect layer does not occur,

said plurality of studs comprising copper atom diffusion barriers.

2. The structure of claim 1, said at least one copper interconnect layer comprising a copper metal line.

3. The structure of claim 1, said plurality of studs comprising copper (Cu).

4. The structure of claim 1, said plurality of studs comprising one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru), manganese (Mn), cobalt (Co), aluminum (Al) and combinations thereof.

5. The structure of claim 1, said plurality of studs protruding only partially into said at least one copper interconnect layer.

6. The structure of claim 1, at least one of said plurality of studs being formed in a contact location of a semiconductor device formed in a substrate underneath said at least one copper interconnect layer.

7. An interconnect structure for an integrated circuit device, said structure comprising:

a metal line formed within a dielectric layer; and

a plurality of metal/alloy studs positioned within said metal line,

said plurality of metal/alloy studs being perpendicular to said metal line and protruding into said metal line from a bottom of said metal line, and

said plurality of metal/alloy studs comprising a grain boundary diffusion barrier for metal atoms in said metal line.

8. The interconnect structure of claim 7, said metal line comprising copper (Cu).

9. The interconnect structure of claim 7, said plurality of metal/alloy studs comprising one of copper (Cu), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru), manganese (Mn), cobalt (Co), aluminum (Al) and combinations thereof.

10. The interconnect structure of claim 7, said plurality of metal/alloy studs being spaced apart by a distance less than or equal to a Blech length of said metal line.

11. The interconnect structure of claim 7, said plurality of metal/alloy studs protruding only partially into said metal line.

12. The interconnect structure of claim 7, said plurality of metal/alloy studs protruding through said metal line.

13. The interconnect structure of claim 7, at least one of said plurality of metal/alloy studs being formed in a contact location of a semiconductor device formed in a substrate underneath said dielectric layer.

14. A method of forming an interconnect structure for an integrated circuit device, the method comprising:

forming a multi-layer substrate having a first layer and a dielectric layer;

forming paths through said first layer and said dielectric layer;

filling said paths with a metallic material;

forming a recess in said dielectric layer such that said metallic material filling said paths protrudes into said recess; and

forming a metal line segment within said recess in said dielectric layer.

15. The method of claim 14, said metal line segment comprising copper (Cu).

16. The method of claim 14, said metallic material comprising one of copper (Cu), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru), manganese (Mn), cobalt (Co), aluminum (Al) and combinations thereof.

17. The method of claim 14, said forming paths through said first layer and said dielectric layer further comprising:

spacing said paths apart by a distance less than or equal to a Blech length of said metal line segment.

18. The method of claim 14, said forming paths through said first layer and said dielectric layer further comprising:

forming at least one path in a contact location of a semiconductor device formed in a substrate underneath one of said first layer and said dielectric layer.

19. The method of claim 14, said forming a recess in said dielectric layer further comprising:

forming said recess such that said metallic material filling said paths protrudes only partially into said recess.

20. A method comprising:

forming a first layer of a multi-layer substrate, said first layer having a plurality of metallic plugs therethrough;

depositing a dielectric layer on said first layer;

forming a recess through said dielectric layer and at least partially through said first layer such that said plurality of metallic plugs protrudes into said recess; and

forming a metal line segment within said recess,

said metallic plugs being perpendicular to said metal line.

21. The method of claim 20, said metal line segment comprising copper (Cu).

22. The method of claim 20, said plurality of metallic plugs comprising one of copper (Cu), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), ruthenium (Ru), manganese (Mn), cobalt (Co), aluminum (Al) and combinations thereof.

23. The method of claim 20, said forming a first layer of a multi-layer substrate further comprising:

spacing said plurality of metallic plugs apart by a distance less than or equal to a Blech length of said metal line segment.

24. The method of claim 20, said forming a first layer of a multi-layer substrate further comprising:

forming at least one of said plurality of metallic plugs in a contact location of a semiconductor device formed in a substrate underneath one of said first layer and said dielectric layer.

25. The method of claim 20, said forming a recess in said dielectric layer further comprising:

forming said recess such that said plurality of metallic plugs protrudes only partially into said recess.