PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

• US 20140054069A1
• Filed: 12/23/2011
• Published: 02/27/2014
• Est. Priority Date: 12/24/2010
• Status: Active Grant

• Current Assignee: LG Innotek Company Limited (LG Corporation)
• Original Assignee: LG Innotek Company Limited (LG Corporation)
• Inventors: Lee, Sang Myung, Yoon, Sung Woon, Lee, Hyuk Soo, Lee, Sung Won, Chun, Ki Do
• Granted Patent: US 9,497,853 B2
• Time in Patent Office: Days
• US Class Current: 174/251
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/098 Special shape of the cross-section of conductors, e.g. very thick plated conductors
• CPC Class Codes: H05K 2203/0323 Working metal substrate or core, e.g. by etching, deforming
• CPC Class Codes: H05K 2203/0376 Etching temporary metallic carrier substrate
• CPC Class Codes: H05K 3/202 using self-supporting metal foil pattern
• CPC Class Codes: H05K 3/4647 by applying an insulating layer around previously made via studs
• CPC Class Codes: H05K 3/465 by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4682 Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Claims

1. A printed circuit board comprising:

a core insulating layer;

at least one via formed through the core insulating layer;

an inner circuit layer buried in the core insulating layer; and

an outer circuit layer on a top surface or a bottom surface of the core insulating layer,

wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width.

2. The printed circuit board of claim 1, wherein the core insulating layer comprises:

a first insulating layer for burying an upper portion of the via from the center part of the via; and

a second insulating layer located below the first insulating layer to bury a lower portion of the via from the center part of the via.

3. The printed circuit board of claim 2, wherein the inner circuit layer is buried in the first insulating layer or the second insulating layer.

4. The printed circuit board of claim 1, wherein the inner circuit layer has a triangular sectional shape.

5. The printed circuit board of claim 1, wherein the inner circuit layer has a rectangular sectional shape.

6. The printed circuit board of claim 1, wherein the via and the inner circuit layer are formed by using a same material.

7. The printed circuit board of claim 1, wherein the via has a hexagonal sectional shape.

8. The printed circuit board of claim 1, wherein the outer circuit layer is filled in a pattern groove formed on a top surface or a bottom surface of the core insulating layer.

9. The printed circuit board of claim 8, wherein the pattern groove has a U-sectional shape.

10. The printed circuit board of claim 1, further comprising an adhesive layer formed on a top surface or a bottom surface of the core insulating layer to expose the via.

11. The printed circuit board of claim 10, wherein the adhesive layer includes primer resin.

12. A printed circuit board comprising:

a core insulating layer;

at least one via formed through the core insulating layer;

an inner circuit layer buried in the core insulating layer; and

an outer circuit layer on a top surface or a bottom surface of the core insulating layer,

wherein a circuit layer including the inner circuit layer and the outer circuit layer has a number of 2n+1 (n is a positive integer).

13. A method for manufacturing a printed circuit board, the method comprising:

forming at least one via and an inner circuit layer by etching a metal substrate;

forming an insulating layer to bury the via; and

forming an outer circuit layer on a top surface or a bottom surface of the insulating layer.

14. The method of claim 13, wherein the forming of the via and the inner circuit layer comprises:

forming a first part of the via and the inner circuit layer by etching an upper portion of the metal substrate;

forming a first insulating layer to bury the first part of the via and the inner circuit layer; and

forming a second part of the via below the first part of the via by etching a lower portion of the metal substrate.

15. The method of claim 14, wherein the forming of the insulating layer comprises:

forming a second insulating layer to bury the second part of the via.

16. The method of claim 13, wherein the forming of the outer circuit layer comprises:

forming a copper foil layer on and under the insulating layer;

forming a photoresist pattern on the copper foil layer; and

forming the outer circuit layer by etching the copper foil layer using the photoresist pattern as a mask.

17. The method of claim 14, wherein a width of a boundary between the first and second parts of the via is larger than a width of a boundary between the via and the insulating layer.

18. The method of claim 14, wherein the forming of the first part of the via comprises:

simultaneously forming the first part of the via and the inner circuit layer such that the inner circuit layer has a triangular sectional shape by wet-etching the metal substrate.

19. The method of claim 14, wherein the forming of the second part of the via comprises:

simultaneously forming the second part of the via and a lower portion of the inner circuit layer by wet-etching a lower portion of the metal substrate.

21. The method of claim 13, wherein the forming of the outer circuit layer comprises:

forming a pattern groove on a top surface or a bottom surface of the insulating layer; and

filling the pattern groove with a conductive material by plating the conductive material.

20. (canceled)

22-27. -27. (canceled)