Isolated Through Silicon Vias in RF Technologies

• US 20140054743A1
• Filed: 07/24/2013
• Published: 02/27/2014
• Est. Priority Date: 08/24/2012
• Status: Active Grant

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Hurwitz, Paul D., Preisler, Edward, Jebory, Hadi
• Granted Patent: US 9,577,035 B2
• Time in Patent Office: Days
• US Class Current: 257/508
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure'"'"'s fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.

Claims

1. A method for providing electrical isolation in a semiconductor substrate, said method comprising:

etching a deep trench isolation loop to a first depth into said semiconductor substrate;

depositing a dielectric material into said deep trench isolation loop;

etching one or more through silicon vias (TSVs) to a second depth into said semiconductor substrate, said one or more TSVs being disposed within a perimeter of said deep trench isolation loop.

2. The method of claim 1, further comprising doping a portion of said semiconductor substrate surrounding said deep trench isolation loop.

3. The method of claim 1, further comprising filling said one or more TSVs with a metallic filler.

4. The method of claim 3, wherein said metallic filler is selected from the group consisting of titanium and tungsten.

5. The method of claim 3, wherein said metallic filler is in direct electrical contact with said semiconductor substrate.

6. The method of claim 1, wherein said one or more TSVs are part of an array of TSVs.

7. The method of claim 1, wherein said dielectric material completely fills said deep trench isolation loop.

8. The method of claim 1, wherein said dielectric material lines said deep trench isolation loop, providing an unfilled portion of said deep trench isolation loop.

9. The method of claim 8, further comprising depositing a filler material over said dielectric material to fill said unfilled portion of said deep trench isolation loop.

10. The method of claim 9, wherein said filler material comprises polysilicon.

11. A structure for providing electrical isolation in a semiconductor substrate, said structure comprising:

a deep trench isolation loop having a first depth disposed in said semiconductor substrate;

a dielectric material disposed in said deep trench isolation loop;

one or more through silicon vias (TSVs), having a second depth, disposed in said semiconductor substrate and within a perimeter of said deep trench isolation loop.

12. The structure of claim 11, further comprising a doped portion of said semiconductor substrate surrounding said deep trench isolation loop.

13. The structure of claim 11, further comprising a metallic filler within said one or more TSVs.

14. The structure of claim 13, wherein said metallic filler is selected from the group consisting of titanium and tungsten.

15. The structure of claim 13, wherein said metallic filler is in direct electrical contact with said semiconductor substrate.

16. The structure of claim 11, wherein said one or more TSVs are part of an array of TSVs.

17. The structure of claim 11, wherein said dielectric material completely fills said deep trench isolation loop.

18. The structure of claim 11, wherein said dielectric material lines said deep trench isolation loop, providing an unfilled portion of said deep trench isolation loop.

19. The structure of claim 18, further comprising a filler material disposed over said dielectric material and filling said unfilled portion of said deep trench isolation loop.

20. The structure of claim 19, wherein said filler material comprises polysilicon.