METHOD AND SYSTEM FOR COORDINATED DATA EXECUTION USING A PRIMARY GRAPHICS PROCESSOR AND A SECONDARY GRAPHICS PROCESSOR

• US 20140055465A1
• Filed: 02/05/2013
• Published: 02/27/2014
• Est. Priority Date: 03/14/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: De Waal, Abraham B., Diercks, Dwight D.
• Granted Patent: US 9,471,952 B2
• Time in Patent Office: Days
• US Class Current: 345/506
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Claims

1. A system for coordinated data execution in a computer system, comprising:

an add in graphics adapter having a graphics processor coupled to a local graphics memory;

an integrated graphics processor coupled to a system memory;

a graphics bus coupling the primary graphics adapter and the integrated graphics processor, wherein the graphics adapter and the integrated graphics processor are configured for coordinated data execution via communication across the graphics bus.

2. The system of claim 1 wherein the integrated graphics processor is integrated into a North bridge of the computer system.

3. The system of claim 2 wherein the integrated graphics processor is configured to use a portion of system memory for dedicated local memory.

4. The system of claim 2 wherein the graphics adapter is detachably coupled to the graphics bus by a connector.

5. The system of claim 2 wherein the graphics adapter is configured to communicate with the local graphics memory via a high speed local bus and the integrated graphics processor is configured to communicate with the system memory via a high speed system memory bus, wherein the graphics adapter communicates with the integrated graphics processor via a low speed graphics bus.

6. The system of claim 2 wherein the integrated graphics processor is configured to perform graphics processing operations that occur in a first portion of a graphics rendering pipeline.

7. The system of claim 2 wherein the graphics adapter is configured to perform graphics processing operations that occur in a second portion of a graphics rendering pipeline.

8. The system of claim 2 wherein the graphics adapter is configured to process commands from a thread that is different from a thread being processed by the integrated graphics processor.

9. The system of claim 1 wherein the integrated graphics processor comprises at least one shader unit.

10. A dual GPU (graphics processor unit) system for coordinated graphics data execution, comprising:

a first GPU coupled to a local graphics memory;

a second GPU coupled to a system memory, the second GPU integrated with a memory controller;

a graphics bus coupling the first GPU and the second GPU, wherein the first GPU and the second GPU are configured for coordinated data execution via communication across the graphics bus.

11. The system of claim 10 wherein the first GPU is configured to perform graphics processing operations that occur in a second portion of a graphics rendering pipeline.

12. The system of claim 11 wherein the graphics operations that occur in the second portion of the graphics pipeline includes anti-aliasing, bump mapping, or texture mapping.

13. The system of claim 10 wherein the second GPU is configured to perform graphics processing operations that occur in a first portion of a graphics rendering pipeline.

14. The system of claim 13 wherein the graphics operations that occur in the first portion of the pipeline includes back face culling, occlusion culling, view frustrum culling, transform, or lighting.

15. The system of claim 10 wherein the second GPU is configured to perform pre-processing operations in conjunction with a CPU.

16. A method for coordinated data execution using a primary graphics processor and a secondary graphics processor, comprising:

executing a graphics application;

dividing graphics operations from the application into a first set of operations and a second set of operations;

processing the first set of operations using a primary graphics processor; and

processing the second set of operations using a secondary graphics processor, wherein the secondary graphics processor is integrated with a North bridge of the computer system, and wherein the primary graphics processor and the secondary graphics processor are coupled via a graphics bus for coordinated data execution.

17. The method of claim 16 wherein the graphics operations are divided into the first set and the second set by using a graphics driver configured to operate with the graphics application.

18. The method of claim 16 further comprising:

performing graphics processing operations that occur in a first portion of a graphics rendering pipeline by using the secondary graphics processor, wherein the graphics operations that occur in the first portion of the pipeline includes back face culling, occlusion culling, view frustrum culling, transform, or lighting.

19. The method of claim 16 further comprising:

performing graphics processing operations that occur in a second portion of a graphics rendering pipeline by using the primary graphics processor, wherein the graphics operations that occur in the second portion of the graphics pipeline includes anti-aliasing, bump mapping, or texture mapping.

20. The method of claim 16 wherein the primary graphics processor is configured to process commands from a thread that is different from a thread being processed by the secondary graphics processor.