Determining A Design Attribute By Estimation And By Calibration Of Estimated Value

• US 20140059508A1
• Filed: 09/03/2013
• Published: 02/27/2014
• Est. Priority Date: 09/22/2006
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Oh, Nahmsuk, Fallah-Tehrani, Peivand, Kasnavi, Alireza, Sripada, Subramanyam
• Granted Patent: US 8,924,906 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute'"'"'s variation relatively accurately.

Claims

1-20. -20. (canceled)

21. A computer-implemented method of performing static timing analysis on a circuit, the method comprising:

executing a static timing analysis algorithm, by a computer, to compute a first base timing delay value of a circuit including first transistors of a first channel length;

executing an estimation algorithm, by the computer, to compute a first estimated timing delay value of the circuit including the first transistors of the first channel length, the estimation algorithm requiring less computation than the static timing analysis algorithm;

determining a ratio between the first timing delay value and the first estimated timing delay value;

executing the estimation algorithm, by the computer, to compute a second estimated timing delay value of the circuit including second transistors of a second channel length; and

obtaining a calibrated version of the second estimated timing delay value by multiplying the ratio to the second estimated timing delay value.

22. The method of claim 21, wherein the estimation algorithm uses one of Elamore delay, D2M, Variational D2M and Fitted Elamore delay.

23. A computer-implemented method of determining changes in a design attribute of a circuit, the method comprising:

computing, by a computer, a first value of a design attribute of a circuit corresponding to a first value of a design parameter of the circuit;

determining a first estimated value of the design attribute corresponding to the first value of the design parameter using an estimation technique; and

determining a calibration function for computing a calibrated value of the first estimate based at least on a first ratio between the first value of the design attribute and the first estimated value of the design attribute, the calibrated value of the first estimate more accurate than the first estimated value of the design attribute.

24. The method of claim 23, further comprising:

determining a second estimated value of the design attribute corresponding to a second value of the design parameter using the estimation technique; and

determining a calibrated value of the second estimate of the design attribute corresponding to the second value of the design parameter based on the calibration function and the second estimated value of the design attribute.

25. The method of claim 24, wherein determining the calibration function comprises:

determining a second ratio by dividing the second value of the design attribute and the second estimated value of the design attribute, and

determining the calibration function by fitting the first ratio and the second ratio to a polynomial function.

26. The method of claim 23, wherein the polynomial function is of a first order.

27. The method of claim 23, wherein the design attribute is one of timing delay of a signal passing through the circuit, crosstalk delay of a signal passing through the circuit, arrival windows of a signal passing through the circuit, timing slack for a signal passing through the circuit, slew rate of a signal passing though the circuit, capacitance of the circuit, resistance of the circuit, and power consumed by the circuit.

28. The method of claim 23, wherein the design parameter is one of channel length, channel width, dielectric thickness, transistor size, metal width, and metal thickness.

29. A non-transitory computer readable medium configured to store instructions, the instructions when executed by a processor cause the processor to:

compute a first value of a design attribute of a circuit corresponding to a first value of a design parameter of the circuit;

determine a first estimated value of the design attribute corresponding to the first value of the design parameter using an estimation technique; and

determine a calibration function for computing a calibrated value of the first estimate based at least on a first ratio between the first value of the design attribute and the first estimated value of the design attribute, the calibrated value of the first estimate more accurate than the first estimated value of the design attribute.

30. The non-transitory computer readable medium of claim 29, further comprising instructions that cause the processor to:

determine a second estimated value of the design attribute corresponding to a second value of the design parameter using the estimation technique; and

determine, a calibrated value of the second estimate of the design attribute corresponding to the second value of the design parameter based on the calibration function and the second estimated value of the design attribute.

31. The non-transitory computer readable medium of claim 30, further comprising instructions that cause the processor to:

determine a second ratio by dividing the second value of the design attribute and the second estimated value of the design attribute, and

determine the calibration function by fitting the first ratio and the second ratio to a polynomial function.

32. The non-transitory computer readable medium of claim 31, wherein the polynomial function is of a first order.

33. The non-transitory computer readable medium of claim 29, wherein the design attribute is one of timing delay of a signal passing through the circuit, crosstalk delay of a signal passing through the circuit, arrival windows of a signal passing through the circuit, a timing slack for a signal passing through the circuit, slew rate of a signal passing through the circuit, capacitance of the circuit, resistance of the circuit, and power consumed by the circuit.

34. The non-transitory computer readable medium of claim 29, wherein the design parameter is one of channel length, channel width, dielectric thickness, transistor size, metal width, and metal thickness.

35. A system for determining changes in a design attribute of a circuit comprising:

a computer processor; and

a non-transitory computer readable medium configured to store instructions, the instructions when executed by the processor cause the processor to;

compute a first value of a design attribute of a circuit corresponding to a first value of a design parameter of the circuit;

determine a first estimated value of the design attribute corresponding to the first value of the design parameter using an estimation technique; and

determine a calibration function for computing a calibrated value of the first estimate based at least on a first ratio between the first value of the design attribute and the first estimated value of the design attribute, the calibrated value of the first estimate more accurate than the first estimated value of the design attribute.

36. The system of claim 35, where in the non-transitory computer readable medium further comprising instructions that cause the processor to:

determine a second estimated value of the design attribute corresponding to a second value of the design parameter using the estimation technique; and

determine, a calibrated value of the second estimate of the design attribute corresponding to the second value of the design parameter based on the calibration function and the second estimated value of the design attribute.

37. The system of claim 36, wherein the non-transitory computer readable medium further comprising instructions that cause the processor to:

determine a second ratio by dividing the second value of the design attribute and the second estimated value of the design attribute, and

determine the calibration function by fitting the first ratio and the second ratio to a polynomial function.

38. The system of claim 37, wherein the polynomial function is of a first order.

39. The system of claim 35, wherein the design attribute is one of timing delay of a signal passing through the circuit, crosstalk delay of a signal passing through the circuit, arrival windows of a signal passing through the circuit, a timing slack for a signal passing through the circuit, slew rate of a signal passing through the circuit, capacitance of the circuit, resistance of the circuit, and power consumed by the circuit.

40. The system of claim 35, wherein the design parameter is one of channel length, channel width, dielectric thickness, transistor size, metal width, and metal thickness.