Thin Film Transistor Array Substrate, Manufacturing Method Thereof, And Display Device
First Claim
1. A manufacturing method of a thin film transistor array substrate, comprising:
- forming a first passivation layer on a substrate formed with a gate scan line, a thin film transistor, a data line, a first display electrode and a board wiring PAD region, and forming a board wiring PAD-region via hole in the first passivation layer above the board wiring PAD region through a first patterning process;
forming a second passivation layer on the substrate formed with the board wiring PAD-region via hole, and forming a pixel-region via hole in the first passivation layer and the second passivation layer above the first display electrode through a second patterning process in such a way that the pixel-region via hole has a top-size smaller than its bottom-size; and
applying a transparent conductive layer on the substrate formed with the pixel-region via hole to form a second display electrode.
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Accused Products
Abstract
A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer (8) on a substrate (1), and forming a board wiring PAD-region via hole (11) in the first passivation layer (8) above the board wiring PAD region (11) through a first patterning process; forming a second passivation layer (16) on the substrate (1) formed with the board wiring PAD-region via hole (11), and forming a pixel-region via hole (15) in the first passivation layer (8) and the second passivation layer (16) above the display electrode (7) through a second patterning process in such a way that the pixel-region via hole (15) has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate (1) formed with the pixel-region via hole (15) to form a second display electrode.
7 Citations
20 Claims
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1. A manufacturing method of a thin film transistor array substrate, comprising:
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forming a first passivation layer on a substrate formed with a gate scan line, a thin film transistor, a data line, a first display electrode and a board wiring PAD region, and forming a board wiring PAD-region via hole in the first passivation layer above the board wiring PAD region through a first patterning process; forming a second passivation layer on the substrate formed with the board wiring PAD-region via hole, and forming a pixel-region via hole in the first passivation layer and the second passivation layer above the first display electrode through a second patterning process in such a way that the pixel-region via hole has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate formed with the pixel-region via hole to form a second display electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A thin film transistor array substrate, comprising:
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a substrate; a gate scan line, a thin film transistor, a data line, a pixel electrode, a common electrode, a board wiring PAD region and a PAD-region via hole formed on the substrate, wherein a passivation layer between the pixel electrode and the common electrode has a pixel-region via hole formed therein, wherein the passivation layer comprises a first passivation layer and a second passivation layer, and the pixel-region via hole has a top-size smaller than its bottom-size. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification