METHOD AND SYSTEMS FOR HIGH-PRECISION PULSE-WIDTH MODULATION

• US 20140062551A1
• Filed: 08/31/2012
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Bhaumik, Wreeju, Gopalrao, Senthil Kumar Devandaya
• Granted Patent: US 8,994,426 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Claims

1. A method for generating high-precision pulse-width modulation, the method comprising:

calibrating a delay line comprising a plurality of delay units to a system clock, each delay unit having a delay that may vary with time;

determining a desired number of partitions of the system clock;

mathematically selecting a subset of the partitions, wherein the subset of the partitions corresponds to a desired amount to shift rising and falling edges of a low-precision pulse-width modulation waveform;

generating the desired shift amount by applying, to the subset of partitions, a calibration code corresponding to the calibrated delay line, wherein the shift amount is less than a period of the system clock; and

applying the shift amount to rising and falling edges of a low-precision pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform having a precision finer than that of the system clock.

2. The method of claim 1, wherein a number of the subset of partitions is P out of 2^M possible partitions, wherein M is an integer greater than or equal to 1 and P is an integer greater than or equal to 1 but less than or equal to 2^M.

3. The method of claim 1, wherein the desired shift amount of P out of 2^M partitions of the system clock is represented using a M-bit digital word stored in a hardware register.

4. The method of claim 1, wherein the desired shift amount of P out of 2^M partitions of the system clock is maintained even though individual delay units may have delays that may vary with time.

5. The method of claim 1, wherein calibrating the delay line to the system clock comprises locking a delay-locked loop to the system clock.

6. The method of claim 5, wherein the delay-locked loop stores information about the calibration code in a digital hardware register.

7. The method of claim 5, further comprising removing an offset delay of the delay-locked loop.

8. The method of claim 5, further comprising splitting the delay-locked loop into a plurality of stages, each stage generating a phase shifted version of a clock cycle.

9. The method of claim 8, further comprising generating a coarse delay using the split delay-locked loop controlled by at least one high-order bit of an M bit word.

10. The method of claim 9, further comprising generating a fine delay using a second delay-line and a multiplier controlled by at least one low-order bit of the M bit word.

11. The method of claim 1, wherein calibrating the delay line comprises selecting n delay units.

12. The method of claim 11, wherein the shift amount is generated by truncating a last M number of bits of a multiplication product of the n delay units and P.

13. The method of claim 12, wherein the delay line is continuously calibrated over a period of time to make the desired shift amounts invariant of time.

14. A system for generating high-precision pulse-width modulation, the system comprising:

a delay-locked loop comprising a plurality of delay units having time-variable delays, the delay-locked loop being locked to a system clock;

control logic for selecting a subset S of the plurality of delay units to thereby generate a time-invariant shift amount having a precision finer than that of the system clock; and

circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

15. The system of claim 14, where the desired time-invariant shift amount is represented by P out of 2^M partitions of the system clock, and wherein the shift amount is represented by a M bit word.

16. The system of claim 15, wherein the control logic comprises a multiplier to multiply the number S with the number P.

17. The system of claim 16, wherein the control logic further comprises a truncating circuit to truncate M bits of a multiplication product to derive the subset S of the variable delay units.

18. The system of claim 17, wherein the shift amount generated is invariant (within M bit precision limits) of process, voltage and temperature by continuously computing the subset S.

19. The system of claim 14, further comprising a digital counter for controlling a delay of the delay-locked loop.

20. The system of claim 14, wherein the delay-locked loop further comprises an offset delay line for removing an offset delay of the delay-locked loop.

21. The system of claim 14, wherein the control logic comprises a control register that provides a binary representation of the number S of the delay units whose cumulative delay is equal to one system clock period.

22. The system of claim 14, wherein the delay-locked loop is split into a plurality of stages, each stage generating a phase shifted version of a clock cycle.

23. The system of claim 22, wherein the stages of the split delay-locked loop are controlled by at least one high-order bit of an M bit word representing P out of 2^M partitions of the system clock.

24. The system of claim 22, further comprising (i) a second delay line identical to that within the delay locked loop and (ii) a multiplier controlled by at least one low-order bit of an M bit word representing P out of 2^M partitions of the system clock, to achieve a high precision of the pulse-width modulation.

25. The system of claim 22, further comprising multiple high-precision channels, each having its own delay line, sharing the same delay-locked loop.

26. The system of claim 14, wherein the trailing edge of the pulse width modulated waveform input to the system is advanced by one system clock cycle to enable the trailing edge of the high precision output to be pulled in with respect to the original pulse width modulated waveform.

27. The system of claim 14, wherein the delay-locked loop is integrated on a chip.