DIAGNOSTICS IN A DISTRIBUTED FABRIC SYSTEM

• US 20140064105A1
• Filed: 11/06/2013
• Published: 03/06/2014
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Anantharam, Sushma, Ghosh, Nirapada, Kamble, Keshav Govind, Leu, Dar-Ren, Mendon, Chandarani J., Pandey, Vijoy, Peethambaram, Nandakumar, Mukharjee, Nilanjan
• Granted Patent: US 9,059,911 B2
• Time in Patent Office: Days
• US Class Current: 370/250
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 43/045 for graphical visualisation of monitoring data
• CPC Class Codes: H04L 43/0811 by checking connectivity
• CPC Class Codes: H04L 43/0817 by checking functioning
• CPC Class Codes: H04L 49/356 for storage area networks
• CPC Class Codes: H04L 49/555 Error detection

Abstract

A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.

Claims

1. A method for managing a distributed fabric system in which at least one scaled-out fabric coupler (SFC) chassis is connected to at least one distributed line card (DLC) chassis over fabric communication links, each fabric communication link connecting one fabric port of the at least one SFC chassis to one fabric port of the at least one DLC chassis, each fabric communication link including a plurality of lanes by which to carry cells, the method comprising:

collecting, by each fabric element chip of each SFC chassis, per-lane statistics for each SFC fabric port of that SFC chassis;

gathering the per-lane statistics collected by each fabric element chip of each SFC chassis by a central agent; and

integrating the per-lane statistics gathered by the central agent into a topology of the entire distributed fabric system for presentation by a user interface.

2. The method of claim 1, further comprising collecting, by each fabric interface of a network processor of each DLC chassis, per-lane statistics for each DLC fabric port of that DLC chassis.

3. The method of claim 2, further comprising gathering, by the central agent, the per-lane statistics collected by each fabric interface of a network processor of each DLC chassis, and wherein the topology presented by the user interface is further integrated with the per-lane statistics collected by each fabric interface of a network processor of each DLC chassis.

4. The method of claim 1, wherein the per-lane statistics include a number of cells received and a number of cells transmitted during a measurement interval.

5. The method of claim 1, wherein the per-lane statistics include a count acquired during a measurement interval of one or more of the following:

unicast cells received and transmitted, multicast cells received and transmitted, and broadcast cells received and transmitted, a count for each different priority level used for each type of received and transmitted cell, a distribution of cells across the plurality of lanes, and utilization of the fabric communication links.

6. The method of claim 1, wherein the per-lane statistics include error statistics of one or more of the following:

received cell errors, transmitted cell errors, PLL (phase-locked loop) errors, cell header errors on received cells, local buffer overflows of different types, 1-bit parity errors, and multiple bit parity errors.

7. The method of claim 1, wherein the per-lane statistics include a count of control cells of different types during a measurement interval.

8. The method of claim 1, further comprising tuning and testing analog-signal attributes of each lane.