SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20140070325A1
• Filed: 08/07/2013
• Published: 03/13/2014
• Est. Priority Date: 09/07/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Weon-Hong, WON, Seok-Jun, SONG, Moon-Kyun
• Granted Patent: US 9,275,993 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device includes a first interface film on a first area of a substrate, the first interface film including a first growth interface film and a second growth interface film on a lower portion of the first growth interface film, a first dielectric film on the first interface film, and a first gate electrode on the first dielectric film.

Claims

1. A semiconductor device comprising:

a first interface film on a first area of a substrate, the first interface film including,

a first growth interface film, and

a second growth interface film on a lower portion of the first growth interface film;

a first dielectric film on the first interface film; and

a first gate electrode on the first dielectric film.

2. The semiconductor device of claim 1, wherein the first growth interface film and the second growth interface film include at least one of silicon oxide and silicon oxynitride.

3. The semiconductor device of claim 1, further comprising:

a second interface film on a second area of the substrate;

a second dielectric film on the second interface film; and

a second gate electrode on the second dielectric film,

wherein the first growth interface film has a first thickness and the second interface film has a second thickness greater than the first thickness.

4. The semiconductor device of claim 3, wherein the first interface film has a third thickness less than the second thickness of the second interface film.

5. The semiconductor device of claim 3, further comprising:

a SiGe layer on a lower portion of the second interface film in the substrate.

6. The semiconductor device of claim 3, wherein the first interface film and the second interface film include at least one of silicon oxide and silicon oxynitride.

7. The semiconductor device of claim 1, wherein a dielectric constant of the first dielectric film is greater than a dielectric constant of the first and second growth interface films.

8. A method for fabricating a semiconductor device comprising:

defining a first area and a second area on a substrate;

growing an interface material layer on the substrate;

forming a dielectric material layer on the interface material layer;

forming a first work function control material layer on the dielectric material layer in the second area of the substrate;

forming a second work function control material layer on the dielectric material layer and the first work function control material layer;

annealing the first work function control material layer and the second work function control material layer;

removing the annealed first and second work function control material layers; and

forming a re-growth interface material layer on a lower portion of the interface material layer in the first area of the substrate by re-growing the interface material layer in a direction of the substrate using an oxygen plasma process.

9. The method for fabricating a semiconductor device of claim 8, further comprising:

forming a SiGe layer in the second area of the substrate before the growing an interface material layer.

10. The method for fabricating a semiconductor device of claim 8, wherein the forming a re-growth interface material layer includes performing the oxygen plasma process at a temperature of 25°

C. to 500°

C.

11. The method for fabricating a semiconductor device of claim 8, wherein the forming a re-growth interface material layer includes performing the oxygen plasma process at a pressure of 0.01 Torr to 10 Torr.

12. The method for fabricating a semiconductor device of claim 8, wherein the forming a re-growth interface material layer includes performing the oxygen plasma process using a process gas of at least one of O₂, N₂O, Ar, and N₂.

13. The method for fabricating a semiconductor device of claim 8, wherein the forming a first work function control material layer comprises forming the first work function control material layer including at least one of Al, Ti, Zr, Hf, and Mg.

14. The method for fabricating a semiconductor device of claim 8, wherein the forming a second work function control material layer comprises forming the second work function control material layer including at least one of La, Ge, Y, Lu, Sr, and Mg.

15. The method for fabricating a semiconductor device of claim 8, wherein the annealing the first work function control material layer and the second work function control material layer comprises forming a barrier layer on the second work function control material layer.

16. The method for fabricating a semiconductor device of claim 8, further comprising:

forming a gate electrode layer on the dielectric material layer.