SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20140077278A1
• Filed: 03/06/2013
• Published: 03/20/2014
• Est. Priority Date: 09/18/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NOZU, Tetsuro
• Granted Patent: US 8,981,470 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The performance of power semiconductor device of partial gate type structure may be improved by providing the source region only adjacent the gate electrodes in the structure, and providing the contact spaced from the gate by the source. The device includes a plurality of field plate electrodes which extend inwardly of the drift layer, a second field plate electrode disposed between the contact and one of the first field plate electrodes, and a gate electrode located between the source and a second one of the first field plate electrode.

Claims

1. A semiconductor device comprising:

a drift layer;

at least two field plate electrodes extending inwardly of the drift layer and spaced there from by an insulating layer;

electrodes extending inwardly of the drift layer and located to either side of each field plate electrode and spaced there from, and from the draft layer, by the insulating layer; and

a gap extending between the insulating layer adjacent one field plate electrode and a second field plate electrode,

wherein a source and a contact are disposed in the gap, and the contact contacts the source and the insulating layer adjacent one of the field plate electrodes.

2. The semiconductor device of claim 1, wherein the source extends from the contact the insulating layer adjacent to a different one of the field plate electrodes.

3. The semiconductor device of claim 1, wherein the second field plate electrode is disposed within the insulating layer in a location between the contact and the field plate electrode.

4. The semiconductor device of claim 3, wherein the second field plate electrode and the contact extend inwardly of the drift layer to a terminal position;

a drain layer is located on the drift layer on a side thereof opposed to the side thereof into which the field plate electrode extends, and;

the distance from the terminal of the field plate electrode to the drain layer is greater than the distance from the terminal of the contact to the drain layers.

5. The semiconductor device of claim 3, wherein a gate electrode is disposed between the source and the field plate electrode.

6. The semiconductor device of claim 5, wherein the gate electrode is spaced from the source and the field plate electrode by the insulating layer.

7. The semiconductor device of claim 1, wherein a gate electrode is located on either side of a field plate electrode located adjacent to a source;

and

a second field plate electrode is located to either side of a field plate electrode disposed adjacent to a contact.

8. The semiconductor device of claim 1, wherein a source electrode contacts the source and the contact, and the source and contact are differently doped.

9. The semiconductor device of claim 8, wherein the source electrode is spaced from the gate electrodes, field plate electrodes and second field plate electrodes, by an insulating layer.

10. The semiconductor device of claim 8, wherein the insulating layer extends partially between the source and the drain layer.

11. The semiconductor device of claim 10, wherein the insulating layer partially extends between the field plate electrode and the source electrode.

12. A semiconductor device comprising:

a first semiconductor layer of the first conductive type;

a second semiconductor layer of the second conductive type formed on the first semiconductor layer;

a first semiconductor region of the first conductive type formed on the second semiconductor layer;

a second semiconductor region of the second conductive type that comes in contact with the first semiconductor region formed on the second semiconductor layer, with the second semiconductor region having a higher concentration of impurity elements than in the second semiconductor layer;

a first electrode that comes in contact with the first semiconductor region, the second semiconductor layer and the first semiconductor layer through a first insulating layer;

a second electrode that comes in contact with second semiconductor region through a second insulating layer;

a third electrode connected to the first semiconductor region as well as the second semiconductor region; and

a fourth electrode electrically connected to the first semiconductor layer.

13. The semiconductor device according to claim 12, further comprising:

a pair of fifth electrodes held in the first semiconductor layer, the first electrode and the second electrode through a third insulating layer, wherein

the first width of the first semiconductor region which is in the horizontal direction of the pair of fifth electrodes respectively, and the second width of the second semiconductor region in this direction are the same.

14. The semiconductor device according to claim 13, wherein

the first length between the lower end of the second semiconductor region and the lower surface of the first semiconductor layer is smaller than the second length between the lower end of the second electrode and lower surface of the first semiconductor layer.

15. The semiconductor device according to claim 12, wherein

the second electrode and a pair of fifth electrodes come in contact with the third electrode.

16. A method of forming a power semiconductor device, comprising:

forming a drift layer;

forming a plurality of first field plate electrodes adjacent to and spaced from one another to extend inwardly of the drift layer;

forming secondary electrode structures on either side of at least two adjacent field plate electrodes; and

on the portion of the drift layer between adjacent field plate electrodes, forming a single contact region and a single source region, such that one of the secondary electrodes is interposed between the source layer and one of the field plate electrodes, and another of the secondary electrodes is disposed between the source and a second one of the first field plate electrodes.

17. The method of forming a power semiconductor device according to claim 16, further including the step of forming an insulating layer over the drift layer;

patterning the insulating layer to form an opening to expose only a portion of a previously doped source region on the drift layer, and;

doping the exposed portion of the source layer differently than the unexposed portion of the source region to form the contact.

18. The method of forming a power semiconductor device according to claim 17, further including the step of, after doping the contact, increasing the size of the opening in the insulating layer to expose at least a portion of the source region in the enlarged opening.

19. The method of forming a power semiconductor device according to claim 17, wherein the secondary electrode interposed between the source and a first field plate electrode is a gate electrode.

20. The method of forming a power semiconductor device according to claim 17, wherein the step of forming the contact includes the step of forming the contact inwardly of the drift layer deeper than the position of an adjacent secondary electrode into the drift layer.