BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES

• US 20140077380A1
• Filed: 09/14/2012
• Published: 03/20/2014
• Est. Priority Date: 09/14/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kim, Juhan, Rashed, Mahbub
• Granted Patent: US 8,823,178 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

Claims

1. A method comprising:

providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and

providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof.

2. The method according to claim 1, further comprising:

providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and

providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

3. The method according to claim 2, further comprising:

providing the bit line structure to have a third tip edge and a third side edge; and

providing the first and second tip edges to be parallel to the third side edge.

4. The method according to claim 2, further comprising:

providing the first side edge, the second side edge, or a combination thereof to be 1.4 to 1.8 times longer than the first tip edge, the second tip edge, or a combination thereof.

5. The method according to claim 2, further comprising:

providing the first side edge to be 50 nm to 60 nm away from the second side edge.

6. The method according to claim 2, further comprising:

providing the first tip edge to be perpendicular to the first side edge, the second tip edge to be perpendicular to the second side edge, or a combination thereof.

7. The method according to claim 1, further comprising:

providing, via the second patterning process, a second bit line structure; and

providing the word line structure, the ground line structure, the power line structure, or a combination thereof between the bit line structure and the second bit line structure.

8. The method according to claim 1, wherein the bit line structure, the word line structure, the ground line structure, and the power line structure are metal 1 layer structures.

9. The method according to claim 8, further comprising:

providing double patterning with respect to the metal1 layer structures using the first and second patterning processes.

10. A device comprising:

a word line structure having a first tip edge and a first side edge;

a ground line structure having a second tip edge and a second side edge, wherein the first side edge faces the second side edge;

a power line structure; and

a bit line structure proximate the word line structure, the ground line structure, and the power line structure.

11. The device according to claim 10, wherein the bit line structure has a third tip edge and a third side edge, and the first and second tip edges are parallel to the third side edge.

12. The device according to claim 10, wherein the first side edge, the second side edge, or a combination thereof are 1.4 to 1.8 times longer than the first tip edge, the second tip edge, or a combination thereof.

13. The device according to claim 10, wherein the first side edge is 50 nm to 60 nm away from the second side edge.

14. The device according to claim 10, wherein the first tip edge is perpendicular to the first side edge, the second tip edge is perpendicular to the second side edge, or a combination thereof.

15. The device according to claim 10, wherein the bit line structure, the word line structure, the ground line structure, and the power line structure are metal1 layer structures.

16. A method comprising:

providing, via a first patterning process, a word line structure having a first tip edge and a first side edge;

providing, via the first patterning process, a ground line structure having a second tip edge and a second side edge, wherein the first side edge faces the second side edge; and

providing, via a second patterning process, a bit line structure proximate the word line structure and the ground line structure.

17. The method according to claim 16, further comprising:

providing the bit line structure to have a third tip edge and a third side edge; and

providing the first and second tip edges to be parallel to the third side edge.

18. The method according to claim 16, further comprising:

providing the first side edge, the second side edge, or a combination thereof to be 1.4 to 1.8 times longer than the first tip edge, the second tip edge, or a combination thereof.

19. The method according to claim 16, further comprising:

providing, via the first patterning process, a power line structure proximate the bit line structure.

20. The method according to claim 19, wherein the bit line structure, the word line structure, the ground line structure, and the power line structure are metal1 layer structures.