QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN

• US 20140084245A1
• Filed: 06/28/2013
• Published: 03/27/2014
• Est. Priority Date: 09/25/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, John H.
• Granted Patent: US 9,601,630 B2
• Time in Patent Office: Days
• US Class Current: 257/20
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/127 Quantum box structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7781 : with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Claims

1. A field effect transistor fabricated on a substrate, the field effect transistor (FET) comprising:

a recessed metal gate formed in the substrate, the recessed metal gate including a gate dielectric and a metal gate electrode;

a metal source region at least partially embedded in the substrate, the metal source region having an enlarged contact area adjacent to a carrier reservoir; and

a metal drain region at least partially embedded in the substrate, the metal drain region having an enlarged contact area adjacent to a carrier reservoir; and

a channel region adjacent to the recessed metal gate and extending between the metal source region and the metal drain region.

2. The transistor of claim 1, wherein, if the transistor is an NFET, the carrier reservoirs include silicon regions doped with phosphorous or silicon phosphide.

3. The transistor of claim 1, wherein, if the transistor is a PFET, the carrier reservoirs include silicon regions doped with boron or boron silicon germanium.

4. The transistor of claim 1 wherein the enlarged contact areas are quantum dots of diameter 10-100 nm.

5. The method of claim 4 wherein, if the transistor is a PFET, the quantum dots are lined with platinum silicide, and if the transistor is an NFET, the quantum dots are lined with nickel silicide, the silicide thicknesses ranging from 1-20 nm.

6. The method of claim 4 wherein, if the transistor is a PFET, the quantum dots are lined with platinum silicide, and if the transistor is an NFET, the quantum dots are lined with a rare earth metal silicide, the silicide thicknesses ranging from 1-20 nm.

7. The method of claim 6 wherein the rare earth metal silicide includes one or more of yttrium silicide or erbium silicide.

8. The transistor of claim 1 wherein the metal gate electrode is made of tungsten and includes a liner of thickness 1-10 nm made of titanium or titanium nitride.

9. The transistor of claim 1 wherein the metal gate electrode is made of copper and includes a liner of thickness 1-10 nm made of tantalum nitride.

10. The transistor of claim 1 wherein the gate dielectric has a high dielectric constant greater than about 4.0.

11. A method of controlling a number of charge carriers in a transistor channel, the method comprising:

forming a transistor having source and drain regions that include doped charge carrier reservoirs for injection of charge into a three-dimensional conducting channel; and

embedding metal quantum dots in the source and drain regions.

12. The method of claim 11 wherein forming the transistor includes forming a recessed metal gate, by

doping a silicon substrate;

selectively removing dopants to form a central recessed area; and

depositing a metal gate in the central recessed area.

13. A method of making a quantum dot transistor, the method comprising:

forming doped silicon source and drain regions between a pair of isolation trenches in a silicon substrate;

forming epitaxial channels;

forming a gate that includes a gate dielectric having a high dielectric constant; and

embedding metal quantum dots in the source and drain regions.

14. The method of claim 13, wherein the embedding includes depositing a first metal layer, and reacting the first metal layer with underlying doped silicon to form different metal silicides for p-type and n-type transistors depending on which dopant is present in the underlying doped silicon.

15. The method of claim 13 wherein the forming the doped source and drain regions includes implanting the substrate with ions to result in a dopant concentration within the range of about 1.0 E19-1.0 E21 atoms/cm³.

16. The method of claim 13 wherein the forming the doped source and drain regions includes incorporating dopants during epitaxial crystal growth to result in a dopant concentration within the range of about 1.0 E19-1.0 E21 atoms/cm³.

17. The method of claim 13 wherein the epitaxial channels are non-planar and the gate wraps around the epitaxial channels.

18. A transistor array layout, comprising:

a first regular surface pattern of quantum dot array elements configured as transistor source and drain regions; and

a second regular surface pattern of gate array elements interspersed alternately among the quantum dot array elements.

19. The transistor array layout of claim 18 wherein the first and second regular surface patterns have different shapes.

20. The transistor array layout of claim 18 wherein shapes of the array elements, as seen from a top plan view, include one or more of circles, ellipses, or polygons.

21. The transistor array layout of claim 18 wherein the array elements are arranged in a periodic lattice structure.