METHOD FOR FABRICATING GLASS SUBSTRATE PACKAGE

• US 20140085842A1
• Filed: 09/25/2013
• Published: 03/27/2014
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Ping-Jung Yang
• Original Assignee: Ping-Jung Yang
• Inventors: Yang, Ping-Jung
• Granted Patent: US 9,615,453 B2
• Time in Patent Office: Days
• US Class Current: 361/760
• CPC Class Codes: H01G 4/129 containing a glassy phase, e.g. glass ceramic
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05688 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/05788 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32151 the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05B 45/60 : Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
• CPC Class Codes: H05K 1/09 : Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H10K 77/10 : Substrates, e.g. flexible substrates
• CPC Class Codes: Y02E 10/549 : Organic PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Claims

1. A substrate comprising:

a solid glass core having a first surface and a second surface opposed to said first surface;

multiple conductors extending through said solid glass core beginning at said first surface and ending at said second surface, wherein one of said conductors has a third surface and a fourth surface, wherein said third surface and said first surface are substantially coplanar, wherein said second surface and said fourth surface are substantially coplanar, wherein one of said conductors comprise a copper-tungsten alloy material, wherein said solid glass core is directly contact with said conductor; and

a first dielectric layer and a first metal layer formed at said first surface, wherein said first metal layer at the first surface is electrically coupled with one of said conductors.

2. The substrate of claim 1, further comprising a second dielectric layer and a second metal layer formed at said second surface, wherein said second metal layer at the second surface is electrically coupled with one of said conductors.

3. The substrate of claim 1, further comprising a chip over said first surface, wherein a contact point of said chip is electrically coupled with one of said conductors.

4. The substrate of claim 1, further comprising a chip over said first surface and an electronic component under said second surface, wherein said chip is electrically coupled to said electronic component through one of said conductors.

5. The substrate of claim 1, further comprising a first chip and a second chip over said first surface, wherein said first chip is connected to said second chip through said metal layer.

6. The substrate of claim 1, further comprising a first chip and a second chip over said first surface, wherein said second chip is over said first chip, wherein said second chip is connected to said metal layer through a through-silicon-via metal layer in said first chip.

7. The substrate of claim 1, further comprising a chip over said first surface and a passive component under said second surface, wherein said chip is electrically coupled to said passive component through one of said conductors.

8. The substrate of claim 1, further comprising a chip over said first surface and a metal bump under said second surface, wherein said chip is connected to a display substrate through said one of said conductors and said metal bump.

9. The substrate of claim 1, further comprising a metal coil over said first surface.

10. The substrate of claim 1, wherein said metal layer comprises a copper layer.

12. The substrate of claim 1, further comprising a second dielectric layer and a fourth metal layer formed at said second surface, wherein said fourth metal layer at the second surface is electrically coupled with one of said conductors.

13. The substrate of claim 1, further comprising a chip over said first surface, wherein a contact point of said chip is electrically coupled with one of said conductors.

14. The substrate of claim 1, further comprising a chip over said first surface and an electronic component under said second surface, wherein said chip is electrically coupled to said electronic component through one of said conductors.

15. The substrate of claim 1, further comprising a first chip and a second chip over said first surface, wherein said first chip is connected to said second chip through said third metal layer.

16. The substrate of claim 1, further comprising a first chip and a second chip over said first surface, wherein said second chip is over said first chip, wherein said second chip is connected to said third metal layer through a through-silicon-via metal layer in said first chip.

17. The substrate of claim 1, further comprising a chip over said first surface and a passive component under said second surface, wherein said chip is electrically coupled to said passive component through one of said conductors.

18. The substrate of claim 1, further comprising a chip over said first surface and a metal bump under said second surface, wherein said chip is connected to a display substrate through said one of said conductors and said metal bump.

19. The substrate of claim 1, further comprising a metal coil over said first surface.

20. The substrate of claim 1, wherein said third metal layer comprises a copper layer.

11. A substrate comprising:

a solid glass core having a first surface and a second surface opposed to said first surface;

multiple conductors extending through said solid glass core beginning at said first surface and ending at said second surface, wherein one of said conductors has a third surface and a fourth surface, wherein said third surface and said first surface are substantially coplanar, wherein said second surface and said fourth surface are substantially coplanar, wherein one of said conductors comprise a first metal layer and a second metal layer coated said first metal layer, wherein said solid glass core is directly contact with said conductor; and

a first dielectric layer and a third metal layer formed at said first surface, wherein said first third layer at the first surface is electrically coupled with one of said conductors.