METHOD FOR IMPLEMENTING A MULTI-CHIP MODULE WITH A HIGH-RATE INTERFACE
First Claim
1. A multi-chip module, comprising:
- a substrate;
a first physical-layer (PHY) chip mounted on the substrate, the first PHY chip comprising a multiplexer and a physical-layer (PHY) circuit;
a second PHY chip mounted on the substrate; and
an interface coupling the first PHY chip to the second PHY chip;
wherein the multiplexer of the first PHY chip is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into a first data stream and a second data stream, to output the first data stream to the PHY circuit of the first PHY chip, and to output the second data stream to the second PHY chip via the interface.
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0 Petitions
Accused Products
Abstract
A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.
9 Citations
20 Claims
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1. A multi-chip module, comprising:
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a substrate; a first physical-layer (PHY) chip mounted on the substrate, the first PHY chip comprising a multiplexer and a physical-layer (PHY) circuit; a second PHY chip mounted on the substrate; and an interface coupling the first PHY chip to the second PHY chip; wherein the multiplexer of the first PHY chip is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into a first data stream and a second data stream, to output the first data stream to the PHY circuit of the first PHY chip, and to output the second data stream to the second PHY chip via the interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A physical-layer (PHY) chip, comprising:
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a multiplexer configured to selectively operate in one of a first mode and a second mode; and a PHY circuit; wherein, in the first mode, the multiplexer is configured to demultiplex a multiplexed data stream received by the PHY chip into a first data stream and a second data stream, to output the first data stream to the PHY circuit, and to output the second data stream to another PHY chip, and, in the second mode, the multiplexer is configured to pass a data stream received by the PHY chip to the PHY circuit; wherein the PHY circuit is configured to convert a data stream from the multiplexer into a physical-layer data signal for transmission on an Ethernet cable. - View Dependent Claims (11, 12, 13)
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14. A multi-chip module, comprising:
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a substrate; a first physical-layer (PHY) chip mounted on the substrate, the first PHY chip comprising a router and a physical-layer (PHY) circuit; a second PHY chip mounted on the substrate; and an interface coupling the first PHY chip to the second PHY chip; wherein the router of the first PHY chip is configured to receive a plurality of data packets from a media access control (MAC) device, to route one or more of the plurality of data packets having a first address to the PHY circuit, and to route one or more of the plurality of data packets having a second address to the second PHY chip via the interface. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification