FAULT DETECTION SYSTEM AND METHOD FOR OVERSPEED PROTECTION SPEED SENSORS

• US 20140111888A1
• Filed: 10/19/2012
• Published: 04/24/2014
• Est. Priority Date: 10/19/2012
• Status: Active Grant

• Current Assignee: GE Infrastructure Technology, LLC (General Electric Company)
• Original Assignee: General Electric Company
• Inventors: Wise, Michael Glynn, Boettner, Fred Henry, Booth, John Robert
• Granted Patent: US 8,796,980 B2
• Time in Patent Office: Days
• US Class Current: 361/23
• CPC Class Codes: F01D 21/02 Shutting-down responsive to overspeed
• CPC Class Codes: F05D 2260/80 Diagnostics
• CPC Class Codes: F05D 2270/021 to prevent overspeed
• CPC Class Codes: F05D 2270/304 Spool rotational speed
• CPC Class Codes: G05B 5/01 electric
• CPC Class Codes: H02P 6/17 and for generating speed information
• CPC Class Codes: H02P 9/006 Means for protecting the generator by using control control effected upon generator excitation circuit to reduce harmful effects of overloads or transients H02P9/10

Abstract

A fault detection system for an over-speed protection system of a rotating machine includes a first speed sensor, second speed sensor, and third speed sensor sensing a speed of a shaft of the rotating machine. The system includes a first input configured to receive a first pulse train from the first speed sensor, a second input configured to receive a second pulse train from the second speed sensor, a third input configured to receive a third pulse train from the third speed sensor, and a processor configured to generate a shutdown signal for the rotating machine based on the first pulse train, the second pulse train, and the third pulse train.

Claims

1. A fault detection system for an over-speed protection system of a rotating machine including a first speed sensor, second speed sensor, and third speed sensor sensing a speed of a shaft of the rotating machine, the system comprising:

a first input configured to receive a first pulse train from the first speed sensor;

a second input configured to receive a second pulse train from the second speed sensor;

a third input configured to receive a third pulse train from the third speed sensor; and

a processor configured to generate a shutdown signal for the rotating machine based on the first pulse train, the second pulse train, and the third pulse train.

2. The system according to claim 1, further comprising:

a first error integrator configured to process the first pulse train and the second pulse train and output a first fault signal;

a second error integrator configured to process the first pulse train and the third pulse train and output a second fault signal; and

a third error integrator configured to process the second pulse train and the third pulse train and output a third fault signal, wherein

the processor generates the shutdown signal for the rotating machine based on the first fault signal, the second fault signal, and the third fault signal.

3. The system according to claim 2, wherein the first error integrator outputs the first fault signal based on a difference in pulse count between the first pulse train and the second pulse train, the second error integrator outputs the second fault signal based on a difference in pulse count between the first pulse train and the third pulse train, and the third error integrator outputs the third fault signal based on a difference in pulse count between the second pulse train and the third pulse train.

4. The system according to claim 3, wherein the processor generates the shutdown signal when two of the first fault signal, the second fault signal, and the third fault signal are output.

5. The system according to claim 3, wherein the processor generates the shutdown signal when all of the first fault signal, the second fault signal, and the third fault signal are output.

6. The system according to claim 1, wherein the processor generates the shutdown signal when at least one among the first pulse train, the second pulse train, and the third pulse train are not received.

7. The system according to claim 1, wherein the processor generates the shutdown signal when at least two among the first pulse train, the second pulse train, and the third pulse train are not received.

8. The system according to claim 1, wherein the processor implements an automatic shutdown of the rotating machine after a time delay following generation of the shutdown signal.

9. A programmable logic device programmed to perform fault detection of an over-speed protection system for a rotating machine including a first speed sensor, second speed sensor, and third speed sensor sensing a speed of a shaft of the rotating machine, the device comprising:

a first input configured to receive a first pulse train from the first speed sensor;

a second input configured to receive a second pulse train from the second speed sensor;

a third input configured to receive a third pulse train from the third speed sensor; and

a processor configured to generate a shutdown signal for the rotating machine based on the first pulse train, the second pulse train, and the third pulse train.

10. The device according to claim 9, further comprising:

a first error integrator configured to process the first pulse train and the second pulse train and output a first fault signal;

a second error integrator configured to process the first pulse train and the third pulse train and output a second fault signal; and

a third error integrator configured to process the second pulse train and the third pulse train and output a third fault signal, wherein

the processor generates the shutdown signal for the rotating machine based on the first fault signal, the second fault signal, and the third fault signal.

11. The device according to claim 10, wherein the first error integrator outputs the first fault signal based on a difference in pulse count between the first pulse train and the second pulse train, the second error integrator outputs the second fault signal based on a difference in pulse count between the first pulse train and the third pulse train, and the third error integrator outputs the third fault signal based on a difference in pulse count between the second pulse train and the third pulse train.

12. The device according to claim 11, wherein the processor generates the shutdown signal when two of the first fault signal, the second fault signal, and the third fault signal are output.

13. The device according to claim 11, wherein the processor generates the shutdown signal when all of the first fault signal, the second fault signal, and the third fault signal are output.

14. The device according to claim 9, wherein the processor generates the shutdown signal when at least one among the first pulse train, the second pulse train, and the third pulse train are not received.

15. The device according to claim 9, wherein the processor generates the shutdown signal when at least two among the first pulse train, the second pulse train, and the third pulse train are not received.

16. The device according to claim 9, wherein the processor implements an automatic shutdown of the rotating machine after a time delay following generation of the shutdown signal.

17. A method, implemented by a processor, of detecting faults in an over-speed protection system of a rotating machine, the method comprising:

determining whether a first pulse train is received from a first speed sensor sensing a first speed of a shaft of the rotating machine;

determining whether a second pulse train is received from a second speed sensor sensing a second speed of the shaft;

determining whether a third pulse train is received from a third speed sensor sensing a third speed of the shaft; and

when a specified number of the first pulse train, the second pulse train, and the third pulse train are determined to not be received, outputting a shutdown signal based on processing the first pulse train, the second pulse train, and the third pulse train.

18. The method according to claim 17, wherein the specified number is two.

19. The method according to claim 17, wherein the specified number is one.

20. The method according to claim 17, wherein the processing the first pulse train, the second pulse train, and the third pulse train includes comparing a number of pulses in the first pulse train with a number of pulses in the second pulse train in a first comparison and with a number of pulses in the third pulse train in a second comparison and comparing the number of pulses in the second pulse train with the number of pulses in the third pulse train in a third comparison.