Dual Mode Power Supply Controller with Charge Balance Multipliers and Charge Balance Multiplier Circuits

• US 20140117964A1
• Filed: 01/04/2013
• Published: 05/01/2014
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: IDEAL Industries Lighting, LLC (Ideal Industries Incorporated)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Walters, Michael, Hu, Qingcong
• Granted Patent: US 9,509,215 B2
• Time in Patent Office: Days
• US Class Current: 323/299
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0016 Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H05B 45/14 using electrical feedback from LEDs or from LED modules
• CPC Class Codes: H05B 45/38 using boost topology
• CPC Class Codes: H05B 45/39 Circuits containing inverter bridges

Abstract

A circuit for generating an output current includes a control signal generating circuit that is configured to generate a control signal. The control signal is a function of a level of an analog input voltage signal, and a level of the output current is a function of a level of an analog input current signal and the level of the analog input voltage signal.

Claims

1. A circuit for generating an output current, comprising:

a control signal generating circuit that is configured to generate a control signal, wherein the control signal is a function of a level of an analog input voltage signal and wherein a level of the output current is a function of a level of an analog input current signal and the level of the analog input voltage signal.

2. The circuit of claim 1, further comprising:

a switched current source that is controlled by the control signal; and

a balance capacitor coupled to the switched current source;

wherein a duty cycle of the control signal is proportional to a level of the analog input voltage signal; and

wherein a level of the output current is proportional to a product of a level of the analog input current signal and the level of the analog input voltage signal.

3. The circuit of claim 2, further comprising:

an output current mirror coupled to the balance capacitor;

wherein the switched current source receives the analog input current signal as an input; and

wherein the balance capacitor is charged by a current output by the switched current source and is discharged through the output current mirror.

4. The circuit of claim 3, further comprising a resistor between the balance capacitor and the output current mirror.

5. The circuit of claim 2, wherein the control signal generating circuit comprises:

a comparator configured to receive the analog input voltage signal and a ramp voltage and to generate the control signal in response to the analog input voltage signal and the ramp voltage; and

a ramp voltage generating circuit coupled to the comparator and configured to generate the ramp voltage.

6. The circuit of claim 5, wherein the ramp voltage generating circuit comprises:

a current source configured to generate a ramping current;

a ramping capacitor coupled to the current source and configured to be charged by the ramping current;

a transistor switch configured to discharge the ramping capacitor in response to a discharge signal; and

a hysteretic comparator configured to compare the ramping voltage with a reference voltage and to generate the discharge signal in response to the comparison of the ramping voltage with the reference voltage.

7. The circuit of claim 5, wherein the current mirror comprises:

a first transistor having a gate terminal and a drain terminal;

a second transistor having a gate terminal coupled to the gate terminal of the first transistor and a drain terminal coupled to the drain terminal of the first transistor; and

a switch transistor coupled between the drain terminals of the first and second transistors and the gate terminals of the first and second transistors, wherein the switch terminal has a gate terminal coupled to an output of the comparator and is configured to receive the control signal.

8. The circuit of claim 2, further comprising an input current conditioning circuit comprising a first current mirror and a second current mirror coupled to the first current mirror, wherein the first current mirror is configured to supply an input current signal as the analog input current signal when the analog input current signal is above a threshold level, and wherein the second current mirror is configured to supply a reference current signal as the analog input current signal when the analog input current signal is below the threshold level.

9. The circuit of claim 2, wherein the multiplier circuit is configured to be switched between a first mode in which the input current signal is nonzero and a second mode in which the input current signal is zero.

10. The circuit of claim 2, further comprising a clamping diode coupled to the balance capacitor.

11. The circuit of claim 2, wherein the output current is given as:

I_PK=(V_COMP*I_CH)/V_LIMIT

where I_PK is the output current, V_COMP is the analog input voltage signal, I_CH is the analog input current signal, and V_LIMIT is a reference voltage.

12. The circuit of claim 11, wherein a charge that is stored in the balance capacitor is given as (I_CH−

I_PK)DTs, where D is a duty cycle of the control signal and Ts is a period of the control signal, and wherein a charge that is discharged from the balance capacitor is given as I_PK(1−

D)Ts.

13. The circuit of claim 2, wherein the switched current source receives a reference current as an input, and wherein the balance capacitor is charged by the analog input current signal and is discharged by the switched current source.

14. The circuit of claim 13, further comprising:

a hysteretic inverter having an input coupled to the balance capacitor; and

a switch coupled to an output of the hysteretic inverter and configured to control the switched current source.

15. The circuit of claim 14, further comprising:

an output inverter having an input coupled to the output of the hysteretic inverter and configured to generate an output signal having an amplitude that is proportional to the analog input voltage signal.

16. The circuit of claim 15, further comprising:

a filter configured to filter the output signal of the output inverter; and

an amplifier configured to amplify the filtered output signal of the output inverter.

17. The circuit of claim 13, wherein the output current signal is given by:

I_PK=I_CH*V_COMP*K

wherein I_PK is the output current, I_CH is the analog input current signal, V_COMP is the analog input voltage signal, and K is a constant.

18. The circuit of claim 17, wherein a charge that is stored in the balance capacitor is given as I_CH(1−

D)Ts, where D is a duty cycle of the control signal and Ts is a period of the control signal, and wherein a charge that is discharged from the balance capacitor is given as (I_FS−

I_CH)DTs, wherein I_FS is the reference current.

19. A power conversion circuit, comprising:

a voltage boost circuit including a boost inductor, the voltage boost circuit being configured to generate an output voltage in response to an input voltage; and

a boost controller configured to control operation of the voltage boost circuit;

wherein the boost controller is configured to generate an error signal my multiplying a current signal and a voltage signal; and

wherein the power conversion circuit further comprises a multiplier circuit for multiplying the current signal by the voltage signal, the multiplier circuit comprising;

a switched current source that is controlled by a control signal;

a control signal generating circuit that is configured to generate the control signal, wherein a duty cycle of the control signal is proportional to a level of the voltage signal; and

a balance capacitor coupled to the switched current source;

wherein a level of the output current is proportional to a product of a level of the current signal and the level of the voltage signal.

20. The power conversion circuit of claim 19, further comprising:

an output current mirror coupled to the balance capacitor;

wherein the switched current source receives the analog input current signal as an input; and

wherein the balance capacitor is charged by a current output by the switched current source and is discharged through the output current mirror.

21. The power conversion circuit of claim 19, wherein the switched current source receives a reference current as an input, and wherein the balance capacitor is charged by the analog input current signal and is discharged by the switched current source.