HIGH FREQUENCY SWITCH CIRCUIT

• US 20140118053A1
• Filed: 10/24/2013
• Published: 05/01/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuno, Noriaki
• Granted Patent: US 9,209,801 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an n^th transistor from a first terminal to a second terminal. First to n^th nodes are connected to gates of the first to n^th transistors. N number of resistance elements are connected in series in an order from a first resistance element to an n^th resistance element from a bias terminal to the n^th node. The first resistance element is connected between said bias terminal and said first node, and the k^th resistance element (k=2 to n) is connected between the (k−1)^th node and the k^th node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.

Claims

1. A high frequency switch circuit comprising:

a first terminal;

a second terminal;

a bias terminal;

n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an n^th transistor from said first terminal to said second terminal;

first to n^th nodes connected to gates of said first to n^th transistors; and

n number of resistance elements connected in series in an order from a first resistance element to an n^th resistance element from said bias terminal to said n^th node,

wherein said first resistance element is connected between said bias terminal and said first node, and

a k^th resistance element (k=2 to n) is connected between said (k−

1)^th node and said k^th node.

2. The high frequency switch circuit according to claim 1, wherein said n^th node is not connected to said second terminal through any element other than said n^th transistor.

3. The high frequency switch circuit according to claim 1, wherein a resistance value of an l^th resistance element (l is any of integers of 2 to n) is higher than that of an (l−

1)^th resistance element.

4. The high frequency switch circuit according to claim 3, wherein the resistance values becomes smaller in an order of from said n^th resistance element to said first resistance element.

5. The high frequency switch circuit according to claim 1, further comprising:

a back gate bias terminal;

first to n^th back gate nodes respectively connected to back gates of said first to n^th transistors; and

n number of back gate resistance elements connected in series in an order from a first back gate resistance element to an n^th back gate resistance element from said back gate bias terminal to said n^th back gate node,

wherein said first back gate resistance element is connected between said back gate bias terminal and said first back gate node, and

a k^th back gate resistance element (k=2 to n) is connected between a (k−

1)^th back gate node and a k^th back gate node.

6. The high frequency switch circuit according to claim 1, wherein said first terminal is a ground terminal to which a ground potential is applied, and

wherein said second terminal is a high frequency signal terminal to which a high frequency signal is applied.

7. A high frequency switch circuit comprising:

a first terminal;

a second terminal;

a bias terminal;

n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an n^th transistor from said first terminal to said second terminal;

first to n^th nodes respectively connected to back gates of said first to n^th transistors; and

n number of resistance elements connected in series in an order from a first resistance element to an n^th resistance element from said bias terminal to said n^th node,

wherein said first resistance element is connected between said bias terminal and said first node, and

a k^th resistance element (k=2 to n) is connected between said (k−

1)^th node and said k^th node.