DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS

• US 20140119099A1
• Filed: 10/31/2013
• Published: 05/01/2014
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., Shifren, Lucian, Roy, Richard S.
• Granted Patent: US 9,431,068 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.

Claims

1. A dynamic random access memory (DRAM), comprising:

at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor;

a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from a power supply voltage of the DRAM; and

peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits having at least one deeply depleted channel (DDC) transistor having a body coupled to receive the body bias voltage, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a dopant concentration that is no less than 1×

10¹⁸ dopant atoms/cm³ and that is different from a dopant concentration of a substrate portion or well containing the DDC transistor.

2. The DRAM of claim 1, wherein:

the peripheral circuits comprise first DDC transistors and second DDC transistors of a same conductivity type, the first DDC transistors having a different threshold voltage than the second DDC transistors.

3. The DRAM of claim 1, wherein:

the peripheral circuits comprises a sense amplifier circuit coupled to the DRAM cell array, and configured to sense data stored by the DRAM cells, the sense amplifier circuit comprising at least a first matching pair of DDC transistors;

wherein

the matching pair of DDC transistors have the same size and conductivity type.

4. The DRAM of claim 3, further including:

a latch circuit coupled to the sense amplifier.

5. The DRAM of claim 3, wherein:

the sense amplifier circuit comprises a second matching pair of DDC transistors of second conductivity type, wherein the drains of the first matching pair of DDC transistors share common sense nodes with the drains of the second matching pair of DDC transistors.

6. The DRAM of claim 4, wherein:

the body bias is used to apply a body bias to at least some of the DDC transistors to impart a change of device sufficient to place the sense amplifier into each of a sensing mode and a data retention mode.

7. The DRAM of claim 6, wherein:

the body bias is used to calibrate fine delay to coarse delay in the sense amplifier.

8. The DRAM of claim 1, further including:

word line drivers configured to drive word lines the DRAM cell array;

a word line voltage regulator circuit configured to generate a word line drive voltage from the bias supply voltage; and

a voltage clamp to clamp at least one bias voltage at a pre-selected operational state.

9. The DRAM of claim 1, wherein:

the peripheral circuits comprise a digital delay line circuit including at least a fine delay circuit having a plurality of delay stages arranged in series, each delay stage including DDC transistors; and

the body bias control circuit is a delay control circuit configured to apply different body biases to the DDC transistors of the delay stages in response to a delay set value.

10. The DRAM of claim 9, wherein:

the body bias control circuit comprises a digital-to-analog converter (DAC) and the delay set value comprises a digital value input to the DAC.

11. The DRAM of claim 9, wherein:

the digital delay line further includes

a coarse delay circuit configured to introduce any of a plurality of coarse delays into an input signal, and

the fine delay circuit introduces any of a plurality of fine delays into the input signal;

wherein

the coarse delays have a same duration, the fine delays have a same duration, and the coarse delays consists of N fine delays, where N is an integer greater than one.

12. A dynamic random access memory (DRAM), comprising:

a DRAM core region formed in a substrate comprising access transistors and storage capacitors; and

a deeply depleted channel (DDC) transistor region formed in the substrate comprising a plurality of DDC transistors in regions separated by isolation structures, each DDC transistor having a screening region of the first conductivity type formed below a substantially undoped channel region, the screening region having a dopant concentration that is no less than 1×

10¹⁸ dopant atoms/cm³ and that is different from a dopant concentration of a substrate or well portion containing the DDC transistor.

13. The DRAM of claim 12, wherein:

the access transistors comprise recessed channel access transistors.

14. The DRAM of claim 12, wherein:

the DDC transistors include first DDC transistors and second DDC transistors of a same conductivity type, the first DDC transistors having a different threshold voltage than the second DDC transistors.

15. The DRAM of claim 14, wherein:

the threshold voltage difference between the first DDC transistors and second DDC transistors arises from any selected from the group of;

a difference in body bias voltage applied to the first DDC transistors as compared to the second DDC transistors and a difference in screening region dopant concentration of the first DDC transistors as compared to the second DDC transistors.

16. The DRAM of claim 14, wherein:

each DDC transistor includes a threshold voltage (Vt) set region of the first conductivity type formed above the screening region and below the substantially undoped channel region, the Vt set region having a dopant concentration less than that of the screening region;

wherein

the threshold voltage difference between the first DDC transistors and second DDC transistors arises from a difference in the dopant concentration of the Vt set region of the first DDC transistors as compared to that of the second DDC transistors.

17. The DRAM of claim 12, wherein:

the DDC transistors include first DDC transistors and second DDC transistors, the first DDC transistors having bodies coupled to receive forward body bias, the second DDC transistors having bodies coupled to receive a reverse body bias.

18. A method of fabricating a dynamic random access memory (DRAM), comprising:

forming screening regions in a substrate, the screening regions having a dopant concentration that is no less than 1×

10¹⁸ dopant atoms/cm³;

forming an epitaxial layer on the substrate;

forming access transistors in a DRAM array region;

forming DDC transistors in a peripheral region that is different from the DRAM array region, each DDC transistor including a gate, source and drain regions corresponding to the gate, the source and drain regions being formed in at least the epitaxial layer and having a substantially undoped channel therebetween, the substantially undoped channels being formed over a screening region; and

forming storage capacitors coupled to the access transistors.

19. The method of claim 18, wherein:

forming the screening regions includes not forming the screening regions in the DRAM array region;

forming the access transistors includes

forming channels in the DRAM array region that extend through the epitaxial layer and into the substrate,

forming an access gate insulator on sides of the channels, and

forming access control gates within the channels.

20. The method of claim 18, further including:

forming conductive paths to bodies of the DDC transistors;

forming a voltage regulator circuit in the peripheral region configured to generate a body bias voltage for application to bodies of the DDC transistors via the conductive paths.