MULTIPLE DATA LINE MEMORY AND METHODS

• US 20140119117A1
• Filed: 10/26/2012
• Published: 05/01/2014
• Est. Priority Date: 10/26/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji, Feeley, Peter Sean, Goda, Akira
• Granted Patent: US 9,093,152 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.

Claims

1. An apparatus comprising:

a plurality of rows of vertical strings of memory cells, each vertical string comprising a respective plurality of memory cells; and

a respective plurality of data lines associated with each row of vertical strings, each data line associated with a respective row being coupled to at least one of the vertical strings in the respective row.

2. The apparatus of claim 1, wherein at least some of the memory cells comprise charge trap transistors.

3. The apparatus of claim 1, wherein at least some of the memory cells comprise floating gate transistors.

4. The apparatus of claim 1, wherein the memory cells of each vertical string are associated with a respective pillar comprising semiconductor material, and each vertical string further comprises a respective source select gate transistor and a respective drain select gate transistor.

5. The apparatus of claim 1, wherein the rows of vertical strings comprise a portion of a block of memory cells.

6. The apparatus of claim 1, further comprising a common source coupled to all of the vertical strings.

7. The apparatus of claim 1, wherein each row of vertical strings is associated with at least four respective data lines, wherein each of the at least four respective data lines is located in a different tier of a semiconductor construction.

8. The apparatus of claim 1, wherein the plurality of rows of vertical strings of memory cells comprise a first row of vertical strings and a second row of vertical strings, wherein the first row of vertical strings comprises:

a first vertical string coupled to a first data line located in a first tier;

a second vertical string adjacent to the first vertical string and coupled to a second data line, the second data line being located in a second tier above the first data line;

a third vertical string adjacent to the second vertical string and coupled to a third data line, the third data line being located in a third tier above the second data line; and

a fourth vertical string adjacent to the third vertical string and coupled to a fourth data line, the fourth data line being located in a fourth tier above the third data line.

9. The apparatus of claim 8, wherein the second row of vertical strings comprises:

a fifth vertical string adjacent to the first vertical string and coupled to a fifth data line;

a sixth vertical string adjacent to the fifth vertical string and coupled to a sixth data line;

a seventh vertical string adjacent to the sixth vertical string and coupled to a seventh data line; and

an eighth vertical string adjacent to the seventh vertical string and coupled to an eighth data line.

10. The apparatus of claim 9, wherein the fifth data line is located in the first tier, the sixth data line is located in the second tier, the seventh data line is located in the third tier, and the eighth data line is located in the fourth tier.

11. The apparatus of claim 10, wherein the sixth vertical string is adjacent to the second vertical string, the seventh vertical string is adjacent to the third vertical string, and the eighth vertical string is adjacent to the fourth vertical string.

12. The apparatus of claim 11, wherein the plurality of rows of vertical strings of memory cells comprises a third row of vertical strings comprising:

a ninth vertical string adjacent to the fifth vertical string and coupled to a ninth data line;

a tenth vertical string adjacent to the ninth vertical string and the sixth vertical string, the tenth vertical string being coupled to a tenth data line;

an eleventh vertical string adjacent to the tenth vertical string and the seventh vertical string, the eleventh vertical string being coupled to an eleventh data line; and

a twelfth vertical string adjacent to the eleventh vertical string and the eighth vertical string, the twelfth vertical string being coupled to a twelfth data line, wherein the ninth data line is located in the first tier, the tenth data line is located in the second tier, the eleventh data line is located in the third tier, and the twelfth data line is located in the fourth tier.

13. The apparatus of claim 12, wherein the first row of vertical strings further comprises:

a thirteenth vertical string adjacent to the fourth vertical string and coupled to the first data line;

a fourteenth vertical string adjacent to the thirteenth vertical string and coupled to the second data line;

a fifteenth vertical string adjacent to the fourteenth vertical string and coupled to the third data line; and

a sixteenth vertical string adjacent to the fifteenth vertical string and coupled to the fourth data line.

14. The apparatus of claim 12, wherein:

the first vertical string, the fifth vertical string and the ninth vertical string are associated with a first drain select gate;

the second vertical string, the sixth vertical string and the tenth vertical string are associated with a second drain select gate;

the third vertical string, the seventh vertical string and the eleventh vertical string are associated with a third drain select gate; and

the fourth vertical string, the eighth vertical string and the twelfth vertical string are associated with a fourth drain select gate.

15. The apparatus of claim 12, further comprising a common source coupled to all of the vertical strings of the plurality of rows.

16. The apparatus of claim 8, wherein the apparatus is configured to perform an operation with respect to only one of the first, second, third and fourth data lines at a time.

17. The apparatus of claim 8, wherein the apparatus is configured to perform an operation with respect to at least two of the first, second, third and fourth data lines simultaneously.

18. The apparatus of claim 17, wherein the apparatus is configured to perform an operation with respect to the first, second, third and fourth data lines simultaneously.

19. The apparatus of claim 8, wherein the apparatus is configured to selectively perform either an operation with respect to only one of the first, second, third and fourth data lines at a time or with respect to at least two of the first, second, third and fourth data lines simultaneously.

20. The apparatus of claim 19, wherein the operation comprises a programming operation.

21. The apparatus of claim 19, wherein the operation comprises a read operation.

22. The apparatus of claim 1, wherein each data line associated with a respective row of vertical strings is located above the respective row of vertical strings.

23. The apparatus of claim 1, wherein each data line associated with a respective row of vertical strings is located below the respective row of vertical strings.

24. An apparatus comprising:

a respective plurality of data lines associated with each row of vertical strings of charge storage devices in a block of charge storage devices, the block comprising a plurality of the rows of vertical strings, each data line associated with a respective row being coupled to at least one of the vertical strings in the respective row of vertical strings; and

a common source coupled to all of the vertical strings of the block.

25. The apparatus of claim 24, wherein each vertical string further comprises:

a respective drain select gate transistor coupled between a respective plurality of the charge storage devices and a respective one of the data lines, to couple the vertical string to the respective data line and to select the vertical string; and

a respective source select gate transistor coupled between the vertical string and the common source, to substantially control conduction between the vertical string and the common source.

26. The apparatus of claim 24, wherein at least some of the charge storage devices comprise multilevel charge storage devices.

27. The apparatus of claim 24, wherein the apparatus comprises a system.

28. The apparatus of claim 24, wherein the apparatus comprises a memory device.

29. The apparatus of claim 28, wherein the memory device comprises a NOT AND (NAND) memory device.

30. An apparatus comprising:

a plurality of tiers of data lines associated with a block of vertical strings of charge storage devices, each vertical string being coupled to a respective one of the data lines; and

a common source coupled to all of the vertical strings of the block.

31. The apparatus of claim 30, wherein each vertical string comprises:

a respective drain select gate transistor coupled between a respective plurality of the charge storage devices and the respective one of the data lines, to couple the vertical string to the respective data line and to select the vertical string; and

a respective source select gate transistor coupled between the vertical string and the common source to substantially control conduction between the vertical string and the common source.

32. The apparatus of claim 31, wherein:

the vertical strings are arranged in rows, each row comprising a plurality of the vertical strings; and

a control gate of the drain select gate transistor of each of the vertical strings in each row is coupled to receive a signal that is separate from signals to be received by control gates of other drain select gate transistors in the row.

33. The apparatus of claim 31, wherein:

the vertical strings are arranged in rows, each row comprising a plurality of the vertical strings; and

for each row, control gates of a first group of the drain select gate transistors are coupled together to receive a first signal and control gates of a second group of the drain select gate transistors are coupled together to receive a second signal separate from the first signal.

34. The apparatus of claim 33, wherein for each row:

a plurality of the drain select gate transistors are coupled to each data line associated with the row;

each vertical string associated with the first group of the drain select transistors is coupled to a different one of the data lines associated with the row; and

each vertical string associated with the second group of the drain select transistors is coupled to a different one of the data lines associated with the row.

35. The apparatus of claim 34, wherein for each row:

control gates of a third group of the drain select gate transistors are coupled together to receive the a third signal separate from the first signal and the second signal; and

each vertical string associated with the third group of the drain select transistors is coupled to a different one of the data lines associated with the row.

36. The apparatus of claim 30, further comprising a sense circuit coupled to each of the data lines to sense the data lines.

37. The apparatus of claim 30, wherein adjacent vertical strings in the block are coupled to different data lines.

38. The apparatus of claim 30, wherein:

the vertical strings are arranged in rows in the block of vertical strings of charge storage devices; and

the plurality of tiers of data lines are associated with each row of vertical strings of charge storage devices, each vertical string being coupled to a respective one of the data lines in the tiers of data lines associated with the row including the vertical string.

39. The apparatus of claim 30, wherein the each vertical string is coupled through a respective contact and a respective contact pad to the respective one of the data lines.

40. The apparatus of claim 39, wherein:

each data line comprises at least one of aluminum and copper;

each contact comprises tungsten; and

each contact pad comprises at least one of aluminum and copper.