INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD
First Claim
1. A method of forming an integrated circuit, comprising:
- forming a first FET and a second FET;
electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate of the second FET; and
connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET to a circuit element, respectively; and
wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant concentration along a channel of the respective FET that includes a peak at a peak location within the channel.
1 Assignment
0 Petitions
Accused Products
Abstract
An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.
1 Citation
16 Claims
-
1. A method of forming an integrated circuit, comprising:
-
forming a first FET and a second FET; electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate of the second FET; and connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET to a circuit element, respectively; and wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant concentration along a channel of the respective FET that includes a peak at a peak location within the channel. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method, comprising:
-
forming a first FET and a second FET, wherein the first FET is a power FET and the second FET is a sense FET; connecting at least one of a source, drain, or gate of the first FET to the corresponding one of a source, drain, or gate of the second FET; connecting at least one further of the source, drain, or gate of the first FET and the corresponding one further of source, drain, or gate of the second FET to a circuit element, respectively; wherein forming the first FET and the second FET include forming a dopant concentration profile of a body along a channel of each of the first and second FETs having a peak at a peak location within the channel, wherein a value of the dopant concentration profile of the body at the peak location of each of the first and second FETs is larger or at least equal to any value of the dopant concentration profile of the body in an extension region that extends into the source, and wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
-
Specification