ARITHMETIC LOGIC UNIT

• US 20140122551A1
• Filed: 10/31/2012
• Published: 05/01/2014
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Dogon, Gil Israel, Arbeli, Yosi, Kreinin, Yosef
• Granted Patent: US 10,318,308 B2
• Time in Patent Office: Days
• US Class Current: 708/201
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K′ bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per word, wherein J′ is less than N multiplied by K′.

Claims

1. An arithmetic logic unit (ALU) comprising:

a first routing grid connected to a plurality of data lanes, wherein the first routing grid is adapted to drive first data to the data lanes;

a second routing grid connected to the data lanes, wherein the second routing grid is adapted to drive second data to the data lanes;

wherein each of the data lanes include a plurality of N functional units with first inputs from the first routing grid and second inputs from the second routing grid wherein the functional units are operable to compute a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs,

wherein each of the data lanes include a reduction unit with inputs adapted to receive K′

bits per word from the functional units, wherein the reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′

bits per word, wherein J′

is less than N multiplied by K′

.

2. The arithmetic logic unit (ALU) of claim 1, wherein the plurality of data lanes includes N data lanes.

3. The arithmetic logic unit (ALU) of claim 1, further comprising:

a global control block configured to control the function of the functional units and to control first routing of the first routing grid and to control second routing of the second routing grid.

4. The arithmetic logic unit (ALU) of claim 1, wherein the function is performed between a datum a of the first data and a datum b of the second data, wherein the function is selected from the group consisting of:

a+b addition, a−

b subtraction, a*b multiplication, a relational operation between a and b and absolute value of a difference ABS(a−

b).

5. The arithmetic logic unit (ALU) of claim 1, wherein the reduction operation is selected from the group consisting of addition, maximum and minimum.

6. The arithmetic logic unit (ALU) of claim 1, wherein the data lanes perform respective computations therein independently from each other.

7. A method for performing any of linear filtering, matrix multiplication, median filtering, local maximum filtering, local minimum filtering and sum of absolute difference filtering using the ALU of claim 1.

8. A computational method performable by an arithmetic logic unit (ALU), the method comprising:

first routing thereby driving first data to a plurality of data lanes;

second routing thereby driving second data to the data lanes; and

in the data lanes;

(i) computing N instances of a function of the respective first data and the respective second data, thereby outputting N results having K′

bits per word;

(ii) performing an operation on the N results thereby outputting an output result having a reduced number J′

bits per word, wherein J′

is less than N multiplied by K′

.

9. The computational method of claim 8, wherein the function is performed between a datum a of the first data and a datum b of the second data, wherein the function is selected from the group consisting of:

a+b addition, a−

b subtraction, a*b multiplication, a relational operation between a and b and absolute value of a difference ABS(a−

b).

10. The computational method of claim 8, further comprising:

controlling the N instances thereby selecting the function and controlling said first routing and second routing.

11. The computational method of claim 8, further comprising:

avoiding storage inside the ALU, of the first and second data.

12. The computational method of claim 8, further comprising:

avoiding storage of intermediate results of the functions of the first and second data.

13. The computational method of claim 8, wherein the computing the N instances are performed independently by the data lanes.