Chip-on-Wafer Structures and Methods for Forming the Same

• US 20140134802A1
• Filed: 01/17/2014
• Published: 05/15/2014
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Lin, Shih Ting, Chang, Hsin
• Granted Patent: US 8,962,481 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81447 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/28 : Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.

Claims

1. A method comprising:

bonding a plurality of dies onto chips of a wafer;

forming trenches in scribe lines of the wafer, wherein the trenches extend from a front surface of the wafer into a semiconductor substrate of the wafer;

molding the plurality of dies with a first dielectric material, wherein the first dielectric material is filled into the trenches;

thinning the substrate from a backside of the wafer, wherein through-vias in the semiconductor substrate are exposed after the thinning; and

forming conductive features on the backside of the wafer, wherein the conductive features are electrically coupled to the through-vias.

2. The method of claim 1 further comprising:

forming a second dielectric material on the backside of the wafer and covering the conductive features; and

patterning the second dielectric material, wherein remaining portions of the second dielectric material comprise;

first portions covering edge portions of the conductive features, with center portions of the conductive features not covered by the second dielectric material; and

second portions aligned to portions of the first dielectric material in the trenches.

3. The method of claim 2, wherein the second dielectric material comprises a photo-sensitive material.

4. The method of claim 1 further comprising, performing a die saw on the wafer to form a package, wherein in the package, a portion of the first dielectric material forms a first ring encircling one of the chips.

5. The method of claim 4, wherein in the package, the ring encircles, and is in contact with, the semiconductor substrate.

6. The method of claim 1, wherein after the thinning the semiconductor substrate, portions of the first dielectric material in the trenches are exposed.

7. The method of claim 1, wherein the first dielectric material comprises a molding compound.

8. A method comprising:

forming trenches in scribe lines of a wafer, wherein the trenches extend from a front surface of the wafer into a substrate of the wafer;

filling a first polymer into the trenches;

thinning the substrate from a backside of the wafer, wherein the first polymer and through-vias in the substrate are exposed after the thinning;

forming conductive features on the backside of the wafer, wherein the conductive features are electrically coupled to the through-vias;

forming a second polymer layer on the backside of the wafer and covering the conductive features; and

patterning the second polymer layer, wherein remaining portions of the second polymer layer comprise first portions covering edge portions of the conductive features, and second portions aligned to portions of the first polymer in the trenches.

9. The method of claim 8, wherein the first portions of the second polymer layer form a plurality of rings disconnected from each other, and wherein the plurality of rings is disconnected from the second portions of the second polymer layer.

10. The method of claim 8 further comprising:

forming Under-Bump-Metallurgies (UBMs) encircled by the first portions of the second polymer layer, wherein the UBMs are coupled to respective underlying ones of the conductive features; and

forming connectors over and aligned to the UBMs.

11. The method of claim 8 further comprising, after the patterning the second polymer layer, performing a die saw on the wafer to form a package, wherein in the package, a portion of the first polymer forms a first ring encircling a chip of the wafer, and the second portions of the second polymer layer form a second ring, and wherein respective outer edges of the first ring and the second ring are aligned to each other.

12. The method of claim 11, wherein the outer edges of the first ring and the second ring are aligned to respective edges of the package.

13. The method of claim 8 further comprising, before the step of filling the first polymer into the trenches, bonding a die onto the wafer, wherein the first polymer further encapsulates the die.

14. The method of claim 8, wherein the first polymer comprises a molding compound, and the second polymer layer comprises a photo-sensitive material.

15. A method comprising:

bonding a plurality of dies onto chips of a wafer;

forming trenches in scribe lines of the wafer, wherein the trenches extend from a front surface of the wafer into a substrate of the wafer;

filling a first dielectric material into the trenches;

thinning the substrate from a backside of the wafer, wherein the first dielectric material and through-vias in the substrate are exposed after the thinning;

forming conductive features on the backside of the wafer, wherein the conductive features are electrically coupled to the through-vias;

covering edge portions of the conductive features and portions of the first dielectric material in the trenches with a second dielectric material; and

forming electrical connectors electrically connected to the conductive features.

16. The method of claim 15, wherein center portions of the conductive features are exposed through the second dielectric material.

17. The method of claim 16 further comprising:

forming Under-Bump-Metallurgies (UBMs) coupled to respective underlying ones of the conductive features, wherein the connectors are electrically coupled to the UBMs.

18. The method of claim 15 further comprising molding the plurality of dies using the first dielectric material, wherein the trenches are filled during the molding.

19. The method of claim 15 further comprising, performing a die saw on the wafer to form a package, wherein in the package, a portion of the first dielectric material in the trenches forms a first ring encircling a chip of the wafer.

20. The method of claim 19, wherein in the package, the second dielectric material forms a second ring, and wherein respective outer edges of the first ring and the second ring are aligned to each other.