SPECULATIVE FINISH OF INSTRUCTION EXECUTION IN A PROCESSOR CORE

• US 20140143523A1
• Filed: 11/16/2012
• Published: 05/22/2014
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: NGUYEN, DUNG Q., STOLT, BENJAMIN W., CHADHA, SUNDEEP, LLOYD, BRYAN, RAY, DAVID S.
• Granted Patent: US 9,384,002 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.

Claims

1. A method of data processing, comprising:

tracking high latency operations of a processor core in entries of a data structure associated with an execution unit of a processor core;

in the execution unit, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishing execution of an instruction dependent on the high latency operation, wherein the speculatively finishing includes reporting an identifier of the entry to completion logic of the processor core and freeing a resource in an execution pipeline of the execution unit utilized by instruction; and

the completion logic recording a dependence of the instruction on the high latency operation and committing an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation.

2. The method of claim 1, wherein:

the processor core includes a completion table including a plurality of entries for tracking instructions, wherein each of the plurality of entries includes a bit vector including multiple bits each corresponding to a respective one of the entries in the data structure that tracks high latency operations;

the recording includes setting a bit in the bit vector corresponding to the entry of the data structure that tracks the high latency operation on which the instruction is dependent.

3. The method of claim 2, and further comprising:

in response to successful completion of the high latency operation, removing a condition of instruction completion from multiple instructions tracked by the completion table by resetting, in all of the multiple bit vectors, the bit corresponding to the entry of the data structure that tracks the high latency operation.

4. The method of claim 1, and further comprising:

in response to unsuccessful completion of the high latency operation;

the completion logic flushing the instruction without committing the execution result to the architected state; and

processor core reissuing the instruction with an indication that speculative finishing of the instruction is inhibited.

5. The method of claim 1, wherein:

the processor core includes an upper level cache;

the execution unit is a load-store execution unit (LSU) that executes memory access instructions;

the data structure is a load miss queue (LMQ);

the instruction is a load-type instruction; and

the high latency operation is a read memory access operation that misses in the upper level cache.

6. The method of claim 5, wherein:

the read memory access operation requests a target memory block; and

the speculatively finishing includes speculatively finishing the load-type instruction in response to receipt by the LSU of a critical data word of the target memory block.

7. The method of claim 1, and further comprising:

after the speculatively finishing and prior to committing the execution result, utilizing the execution resource to execute another instruction.

8. A processor core, comprising:

a data structure including multiple entries for tracking high latency operations associated with instructions executed by the processor core;

an execution pipeline that executes instructions, wherein the execution pipeline, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishes execution of an instruction dependent on the high latency operation by reporting an identifier of the entry and freeing a resource in the execution pipeline utilized by instruction; and

completion logic that, responsive to the identifier of the entry, records a dependence of the instruction on the high latency operation and commits an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation.

9. The processor core of claim 8, wherein:

the processor core includes a completion table including a plurality of entries for tracking instructions, wherein each of the plurality of entries includes a bit vector including multiple bits each corresponding to a respective one of the entries in the data structure that tracks high latency operations;

the completion logic records the dependence of the instruction on the high latency operation by setting a bit in the bit vector corresponding to the entry of the data structure that tracks the high latency operation on which the instruction is dependent.

10. The processor core of claim 9, wherein the completion logic, in response to successful completion of the high latency operation, removes a condition of instruction completion from multiple instructions tracked by the completion table by resetting, in all of the multiple bit vectors, the bit corresponding to the entry of the data structure that tracks the high latency operation.

11. The processor core of claim 8, wherein the completion logic, in response to unsuccessful completion of the high latency operation, flushes the instruction without committing the execution result to the architected state and causes the processor core to reissue the instruction with an indication that speculative finishing of the instruction is inhibited.

12. The processor core of claim 8, wherein:

the processor core includes an upper level cache;

the execution pipeline is a load-store execution pipeline that executes memory access instructions;

the data structure is a load miss queue (LMQ);

the instruction is a load-type instruction; and

the high latency operation is a read memory access operation misses in the upper level cache.

13. The processor core of claim 12, wherein:

the read memory access operation requests a target memory block; and

the load-store pipeline speculatively finishes the load-type instruction in response to receipt by the processor core of a critical data word of the target memory block.

14. The processor core of claim 8, wherein the execution pipeline, after speculatively finishing the instruction and prior to commitment of the execution result, utilizes the execution resource to execute another instruction.

15. A data processing system, comprising:

the processor core of claim 8;

a cache memory coupled to the processor core;

a system fabric coupled to the cache memory; and

a memory interface coupled to the system fabric.

16. The data processing system of claim 15, wherein the processor core, cache memory, system fabric and memory interface are integrated within a system-on-a-chip.

17. A design structure tangibly embodied in a machine-readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processor core, including;

a data structure including multiple entries for tracking high latency operations associated with instructions executed by the processor core;

an execution pipeline that executes instructions, wherein the execution pipeline, prior to completion of a high latency operation tracked by an entry of the data structure, speculatively finishes execution of an instruction dependent on the high latency operation by reporting an identifier of the entry and freeing a resource in the execution pipeline utilized by instruction; and

completion logic that, responsive to the identifier of the entry, records a dependence of the instruction on the high latency operation and commits an execution result of the instruction to an architected state of the processor core only after successful completion of the high latency operation.

18. The design structure of claim 17, wherein the design structure comprises a hardware description language (HDL) design structure.