COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE

• US 20140151807A1
• Filed: 12/05/2012
• Published: 06/05/2014
• Est. Priority Date: 12/05/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chi, Min-hwa, Juengling, Werner
• Granted Patent: US 8,772,117 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

Claims

1. A device, comprising:

a substantially un-doped layer of a semiconducting material;

a plurality of trenches defined in said substantially un-doped layer of semiconducting material, said trenches defining a plurality of fins;

a gate insulation layer positioned on said fins and on a bottom surface of said trenches;

a gate electrode positioned on said gate insulation layer; and

a device isolation structure defined in said substantially un-doped layer of semiconducting material.

2. The device of claim 1, wherein said bottom surface of said trenches defines a planar channel region for said device.

3. The device of claim 1, wherein said substantially un-doped layer of semiconducting material is one of a layer of eptiaxially deposited silicon or an un-doped active layer of a silicon-on-insulator structure.

4. The device of claim 1, further comprising a doped buffer layer positioned adjacent said substantially un-doped layer of semiconducting material.

5. The device of claim 4, wherein said doped buffer layer comprises at least carbon as a dopant material.

6. The device of claim 5, wherein said doped buffer layer further comprises at least one of fluorine and nitrogen as a dopant material.

7. The device of claim 1, wherein said gate insulation layer and said gate electrode fill each of said plurality of trenches.

8. The device of claim 1, wherein said gate insulation layer is comprised of silicon dioxide and said gate electrode is comprised of polysilicon.

9. The device of claim 1, wherein said substantially un-doped layer of semiconductor material is a substantially un-doped layer of epitaxially grown silicon.

10. The device of claim 1, wherein said trenches extend to a depth that is approximately one-half of an overall thickness of said layer of semiconducting material.

11. A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising:

identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device;

performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of semiconducting material;

forming a gate insulation layer on said plurality of fins and on a bottom surface of each of said trenches; and

forming a gate electrode above said gate insulation layer.

12. The method of claim 11, wherein said bottom surface of said trenches defines a planar channel region for said device.

13. The method of claim 11, wherein performing said at least one process operation comprises performing an etching process.

14. The method of claim 11, wherein said substantially un-doped layer of semiconducting material is a layer of epitaxially deposited substantially un-doped silicon.

15. The method of claim 11, wherein said substantially un-doped layer of semiconducting material is an active layer of an SOI substrate.

16. The method of claim 11, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material.

17. The method of claim 11, wherein said gate insulation layer and said gate electrode fills said plurality of trenches.

18. A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising:

forming a buffer layer comprised of at least carbon in a substrate;

performing an epitaxial deposition process to form a substantially un-doped layer of epitaxial silicon above said buffer layer;

identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device;

performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of epitaxial silicon;

forming a gate insulation layer on said plurality of fins and on a bottom of each of said trenches; and

forming a gate electrode above said gate insulation layer.

19. The method of claim 18, wherein performing said at least one process operation comprises performing an etching process.

20. The method of claim 18, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of epitaxial silicon.

21. A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises:

identifying a target threshold voltage for said combination device;

identifying at least one of a target top width of each of said fins or a target thickness of said substantially planar FET device portions such that, during operation, said combination device is intended to exhibit said target threshold voltage;

forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness;

forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions; and

forming a gate electrode above said gate insulation layer

22. The method of claim 21, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is greater than a target threshold voltage for said substantially planar FET device portions.

23. The method of claim 21, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is less than a target threshold voltage for said substantially planar FET device portions.

24. The method of claim 21, wherein said target threshold voltage for said combination device comprises a target threshold voltage for said FinFET device portions that is substantially equal to a target threshold voltage for said substantially planar FET device portions.

25. The method of claim 21, wherein said bottom surface of said trenches defines said upper surface of said substantially planar FET device portions.

26. The method of claim 21, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material.

27. The method of claim 21, wherein said gate insulation layer and said gate electrode fills said plurality of trenches.

28. A method of forming a combination device in a substantially un-doped layer of semiconducting material, wherein said combination device is comprised of a plurality of spaced-apart FinFET device portions, each of which are comprised of at least one fin, and a plurality of substantially planar FET device portions, wherein the method comprises:

identifying a target threshold voltage that is the same for said FinFET device portions and said substantially planar FET device portions;

identifying a target top width of each of said fins such that, during operation, said FinFET device portions are intended to exhibit said target threshold voltage;

identifying a target thickness of said substantially planar FET device portions such that, during operation, said planar FET portions are intended to exhibit said target threshold voltage;

forming a plurality of trenches in said substantially un-doped layer of semiconducting material so as to define said plurality of fins and said substantially planar FET device portions, wherein each of said fins have a top width that is approximately equal to said target top width, and said substantially planar FET device portions have a thickness that is approximately equal to said target thickness;

forming a gate insulation layer on said plurality of fins and on an upper surface of said substantially planar FET device portions; and

forming a gate electrode above said gate insulation layer.

29. The method of claim 28, wherein said bottom surface of said trenches defines said upper surface of said substantially planar FET device portions.

30. The method of claim 28, wherein a depth of said trenches is equal to approximately one-half of a thickness of said substantially un-doped layer of semiconducting material.

31. The method of claim 28, wherein said gate insulation layer and said gate electrode fills said plurality of trenches.

32. A device, comprising:

a substantially un-doped layer of a semiconducting material having an initial thickness;

a plurality of trenches defined in said substantially un-doped layer of semiconducting material, said trenches defining a plurality of fins, each of said fins having a top width dimension that is different than a thickness of said substantially un-doped layer of semiconducting material at a bottom of at least one of said trenches;

a gate insulation layer positioned on said fins and on a bottom surface of said trenches;

a gate electrode positioned on said gate insulation layer; and

a device isolation structure defined in said substantially un-doped layer of semiconducting material.

33. The device of claim 32, wherein said bottom surface of said trenches defines a planar channel region for said device.

34. The device of claim 32, wherein said substantially un-doped layer of semiconducting material is one of a layer of epitaxially deposited silicon or an un-doped active layer of a silicon-on-insulator structure.

35. The device of claim 32, further comprising a doped buffer layer positioned adjacent said substantially un-doped layer of semiconducting material.

36. The device of claim 35, wherein said doped buffer layer comprises at least carbon as a dopant material.

37. The device of claim 36, wherein said doped buffer layer further comprises at least one of fluorine and nitrogen as a dopant material.

38. The device of claim 32, wherein said gate insulation layer and said gate electrode fill each of said plurality of trenches.

39. The device of claim 32, wherein said top width is greater than said thickness of said substantially un-doped layer of semiconducting material at a bottom of at least one of said trenches.

40. The device of claim 32, wherein said top width is less than said thickness of said substantially un-doped layer of semiconducting material at a bottom of at least one of said trenches.