SEQUENTIAL ACCESS MEMORY WITH MASTER-SLAVE LATCH PAIRS AND METHOD OF OPERATING

• US 20140153341A1
• Filed: 12/04/2012
• Published: 06/05/2014
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Alfieri, Robert A.
• Granted Patent: US 9,685,207 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Claims

1. A synchronous sequential access latch array generated by an automated system for generating master-slave latch structures, said latch array comprising:

N/2 rows of master-slave pairs wherein N is equal to the number of addresses that are included in said latch array;

an N/2 to 1 multiplexer coupled to said N/2 rows of master-slave pairs; and

control logic.

2. The latch array of claim 1 wherein said automated system is a logic gate synthesis system that automatically generates master-slave latch structures.

3. The latch array of claim 2 wherein said logic gate synthesis system is invoked from a logic gate synthesis system that generates FIFO structures based on configuration parameter settings.

4. The latch array of claim 1 wherein said control logic is configured to implement data flow to fill latch pairs of respective rows in sequence from row 1 to row N.

5. The latch array of claim 1 wherein said control logic is configured to implement data flow to fill the master latch of respective rows in sequence from row 1 to row N.

6. The latch array of claim 1 wherein said control logic is operable wherein data received by said latch array flows from a master latch in a first half of a clock cycle to a slave latch in a second half of a subsequent clock cycle.

7. The latch array of claim 1 wherein master and slave latches of said latch array comprise random access memory (RAM) addresses.

8. The latch array of claim 1 wherein master and slave latches of said latch array are separately enabled.

9. The latch array of claim 1 providing fully-registered flow control.

10. The latch array of claim 1 being a flow control component of a graphics processing unit (GPU).

11. A method of operating a sequential access memory comprising a master-slave latch pair array, the method comprising:

in a second half of a clock cycle, receiving data into an empty and open master latch in a first row of said master-slave latch pair array, if master-slave latch pairs of other rows are empty or if master-slave latch pairs of other rows are full,

or receiving data into an empty master latch of a subsequent row of said master-slave latch pair array if a master latch and a slave latch of a row or rows preceding said subsequent row are full;

in a first half of a cycle subsequent to a clock cycle in which data is received by a master latch in a row of said master-slave latch pair array, receiving data into a slave latch of said row of said master-slave latch pair array; and

providing access to said data received by said slave latch of said row of said master-slave latch pair array.

12. The method of claim 11 wherein slave latches of said sequential access memory are maintained open and data received by said slave latches flow from master latches of said sequential access memory into said slave latches uninhibited.

13. The method of claim 11 wherein said sequential access memory has N/2 rows where N is equal to the number of addresses in said sequential access memory.

14. The method of claim 11 wherein said providing access to said data comprises using an N/2:

1 multiplexor.

15. The method of claim 11 wherein said sequential access memory provides fully registered flow control.

16. The method of claim 11 wherein said sequential access memory is a FIFO buffer.

17. The method of claim 11 wherein said sequential access memory is a part of a GPU.

18. A method of operating a sequential access memory comprising a master-slave latch pair array, the method comprising:

receiving data into respective master latches in a second half of first respective clock cycles, wherein data that is received in said second half of said first respective clock cycles is allowed to flow uninhibited from respective master latches to respective corresponding slave latches;

receiving data into respective master latches in a second half of second respective clock cycles; and

providing access to data in said respective corresponding slave latches.

19. The method of claim 18 wherein said sequential access memory has N/2 rows where N is equal to the number of latches in said sequential access memory.

20. The method of claim 18 said providing access to said data comprises using an N/2:

1 multiplexor.