DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS

• US 20140159168A1
• Filed: 02/11/2014
• Published: 06/12/2014
• Est. Priority Date: 06/26/2012
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TOH, Eng Huat, TAN, Shyue Seng
• Granted Patent: US 9,064,951 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.

Claims

1. A device comprising:

a substrate;

a source and a drain in the substrate, separated by a ground plane layer;

a channel layer over the ground plane layer, the channel layer being formed after all high thermal steps are performed to the device;

a gate electrode over the channel layer; and

a high-k layer on side surfaces of the gate electrode and between the channel layer and the gate electrode.

2. The device according to claim 1, wherein the channel layer is formed in a recess in the substrate above at least part of the ground plane layer.

3. The device according to claim 2, further comprising a halo layer separating the channel layer from the ground plane layer, the source, and the drain.

4. The device according to claim 3, wherein the halo layer is epitaxially formed of silicon (Si), silicon germanium (SiGe), or germanium (Ge) and has a thickness of between 5 nanometers (nm) and 20 nm.

5. The device according to claim 1, wherein the channel layer is formed of multiple layers including a layer of intrinsic Si on a layer of intrinsic SiGe or intrinsic silicon carbon (Si:

C).

6. The device according to claim 1, further comprising, in the substrate, a depleted layer of SiGe, Si:

C, silicon germanium tin (SiGeSn), germanium tin (GeSn), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphorus (InP), wherein the channel layer is epitaxially formed of intrinsic Si, intrinsic SiGe, or intrinsic Ge.

7. The device according to claim 1, further comprising, in the substrate, a depleted layer of a different material than the source, the drain, the substrate, or a combination thereof, wherein the channel layer is formed of an element or compound consisting of one or more elements from groups III, IV, and V, and wherein all steps subsequent to the forming of the channel layer have temperatures below 600 degrees Celsius (°

C.).

8. The device according to claim 1, further comprising, in the substrate, a depleted layer having a thickness of between 3 nm and 30 nm, wherein the ground plane layer has a thickness of between 10 nm and 100 nm, the channel layer has a thickness of between 3 nm and 30 nm, and high thermal steps have temperatures exceeding 700°

C.

9. A device comprising:

a substrate;

a source and a drain in the substrate, separated by a ground plane layer;

a channel layer epitaxially formed directly on the ground plane layer, the channel layer being formed after all high thermal steps are performed to the device;

a gate electrode over the channel layer; and

a high-k layer on side surfaces of the gate electrode and between the channel layer and the gate electrode.

10. The device according to claim 9, wherein the channel layer is formed in a recess in the substrate, the recess being above at least part of the ground plane layer.

11. The device according to claim 10, wherein the recess in the substrate above has a depth of between 2 nanometers (nm) and 70 nm.

12. The device according to claim 11, wherein the channel layer has an upper surface coplanar with an upper surface of the substrate.

13. The device according to claim 12, wherein the channel layer has an outer side surface coplanar with an outer side surface of the high-k layer.

14. The device according to claim 13, wherein a portion of the high-k layer is formed directly on an upper surface of the channel layer.

15. A device comprising:

a substrate;

a source and a drain in the substrate, separated by a ground plane layer;

a depleted layer on the ground plane, the depleted layer separating the source and drain;

a channel layer on the depleted layer, the channel layer being formed after all high thermal steps are performed to the device;

a gate electrode over the channel layer; and

a high-k layer on side surfaces of the gate electrode and between the channel layer and the gate electrode.

16. The device according to claim 15, wherein the channel layer has a lower surface coplanar with an upper surface of the substrate.

17. The device according to claim 16, wherein the channel layer has an outer side surface coplanar with an outer side surface of the high-k layer.

18. The device according to claim 17, wherein a portion of the high-k layer is formed directly on an upper surface of the channel layer.

19. The device according to claim 15, wherein the channel layer has a thickness of between 3 nanometers (nm) and 30 nm.

20. The device according to claim 15, wherein the channel layer is epitaxially formed directly onto the depleted layer.