Semiconductor Device and Method of Manufacture Thereof

• US 20140159220A1
• Filed: 02/13/2014
• Published: 06/12/2014
• Est. Priority Date: 01/18/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Willkofer, Stefan, Wahl, Uwe, Knott, Bernhard, Hammer, Markus, Strasser, Andreas
• Granted Patent: US 9,269,654 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19102 : in a stacked assembly with the semiconductor or solid state device
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor

Abstract

A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip.

Claims

1. A semiconductor package comprising:

a first semiconductor chip comprising a first coil disposed over a first substrate;

an isolating film disposed on the first semiconductor; and

a second semiconductor chip comprising a second coil disposed over a second substrate, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip to form a coreless transformer.

2. The semiconductor package according to claim 1, wherein the thickness of the second substrate is less than the thickness of the first substrate.

3. The semiconductor package according to claim 1, wherein the dielectric strength of the isolating film is at least 60 kV/mm.

4. The semiconductor package according to claim 1, wherein the dielectric strength of the isolating film is less than 100 kV/mm.

5. The semiconductor package according to claim 1, wherein the isolating film comprises a double side adhesive or a attach paste.

6. The semiconductor package according to claim 1, wherein the isolating film comprises a thickness of 20 μ

m to 500 μ

m.

7. The semiconductor package according to claim 1, wherein the first semiconductor chip comprises an integrated circuit and wherein the second semiconductor chip consists essentially of a second pad, the second coil and an electrical connection between the second pad and the second coil.

8. The semiconductor package according to claim 1, further comprising a lead frame, wherein a first pad of the first semiconductor chip is wire bonded to the lead frame, and wherein a second pad of the second semiconductor chip is wire bonded to the lead frame.

9. A semiconductor package comprising:

a lead frame;

a first semiconductor chip comprising a first coil disposed over a first substrate, the first semiconductor chip disposed on the lead frame;

a second semiconductor chip comprising a second coil disposed over a second substrate, the second coil aligned with the first coil, the second semiconductor chip disposed on the first semiconductor chip;

an isolating film disposed between the first semiconductor chip and the second semiconductor chip, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip to form a coreless transformer; and

an encapsulation material encapsulating the first semiconductor chip, the second semiconductor chip and the lead frame.

10. The semiconductor package according to claim 9, wherein the dielectric strength of the isolating film is at least 60 kV/mm.

11. The semiconductor package according to claim 9, wherein the dielectric strength of the isolating film is less than 100 kV/mm.

12. The semiconductor package according to claim 9, wherein the first semiconductor chip comprises an integrated circuit and wherein the second semiconductor chip consists essentially of a pad, the second coil and an electrical connection between the pad and the second coil.

13. The semiconductor package according to claim 9, wherein the first semiconductor chip and the second semiconductor chip are arranged in a face-to-face configuration.

14. The semiconductor package according to claim 9, wherein the second semiconductor chip comprises a through-via through the second substrate so that the through-via exposes a pad of the second semiconductor chip.

15. The semiconductor package according to claim 14, wherein the second substrate comprises a thickness of less than 300 μ

m.

16. The semiconductor package according to claim 14, further comprising a first wire connection between the lead frame and the pad of the second semiconductor chip and a second wire connection between the lead frame and a pad of the first semiconductor chip.

17. The semiconductor package according to claim 16, wherein there is no wire connection between the first semiconductor chip and the second semiconductor chip.

18. The semiconductor package according to claim 16, wherein the pad of the first semiconductor chip is disposed on a top surface of the first semiconductor chip.

19. The semiconductor package according to claim 9, wherein the first substrate of the first semiconductor chip is connected via a metal bond to the lead frame.

20. The semiconductor package according to claim 9, wherein the first substrate of the first semiconductor chip is connected via an adhesive bond to the lead frame.

21. The semiconductor package according to claim 9, further comprising a third semiconductor chip, the third semiconductor chip encapsulated with the encapsulation material.

22. A semiconductor package comprising:

a first semiconductor chip with a first coil disposed over a first substrate;

a second semiconductor chip with a second coil and a contact pad disposed over a second substrate; and

an isolating film disposed between the first semiconductor chip and the second semiconductor chip, wherein the second semiconductor chip is attached to the first semiconductor chip with the isolating film, wherein the first coil of the first semiconductor chip is inductively coupled through the isolating film with the second coil of the second semiconductor chip;

a through hole disposed in the second substrate and exposing the contact pad;

a wire disposed within the through hole; and

a wire bond disposed in the through hole coupling the wire to the contact pad of the second semiconductor chip.

23. The semiconductor package according to claim 22, wherein the wire couples the second coil to a lead of a lead frame.

24. The semiconductor package according to claim 22, further comprising an encapsulation material encapsulating the first semiconductor chip, the second semiconductor chip, the isolating film, the wire, and the wire bond.