INTEGRATED CIRCUIT INCLUDING CIRCUITS DRIVEN IN DIFFERENT VOLTAGE DOMAINS

• US 20140159773A1
• Filed: 12/09/2013
• Published: 06/12/2014
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Ken Keon Shin
• Inventors: SHIN, Ken Keon
• Granted Patent: US 9,325,314 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/0175 Coupling arrangements; Interface arrangements interface arrangements for digital computers G06F3/00, G06F13/00

Abstract

Provided is an integrated circuit including circuits driven in different voltage domains. The integrated circuit includes a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level, and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level. The memory circuit includes a circuit configured to interface with the logic circuit, configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level. The first power supply voltage corresponds to a first voltage domain, and the second power supply voltage corresponds to a second voltage domain.

Claims

1. An integrated circuit comprising:

a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and

a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit,

wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level.

2. The integrated circuit of claim 1, wherein the logic circuit is configured to generate the signal to read and write from and to the memory circuit.

3. The integrated circuit of claim 1, wherein the circuit comprises:

an interface circuit configured to receive the signal having the first power supply voltage level; and

a clocked gate configured to generate the output signal of the circuit in response to the signal and a clock signal.

4. The integrated circuit of claim 3, wherein the interface circuit comprises:

a first circuit unit connected between the second power supply voltage and a first node, the first circuit unit configured to be supplied with power at the second power supply voltage level according to the output signal of the clocked gate, and configured to receive the signal;

a second circuit unit connected between the second power supply voltage and the first node, and the second circuit unit configured to receive the clock signal;

a third circuit unit connected between the first node and a ground voltage having a ground voltage level, and configured to receive the signal and the clock signal; and

a fourth circuit unit configured to be driven by the second power supply voltage, to receive a signal of the first node, and to output an output signal of a second circuit area.

5. The integrated circuit of claim 4, wherein the clock signal is a signal that operates at the second power supply voltage level and the ground voltage level.

6. The integrated circuit of claim 1, wherein the memory circuit further comprises a plurality of memory cells, and an address decoder configured to decode address signals that address the plurality of memory cells and interface with the logic circuit.

7. The integrated circuit of claim 6, wherein the address decoder is configured to receive the address signals from the logic circuit, and shift levels of the address signals from the first power supply voltage level to the second power supply voltage level.

8. The integrated circuit of claim 1, wherein the memory circuit further comprises a plurality of memory cells each connected to a pair of bit-lines, a sense amplifier unit connected to the bit-lines and which is configured to sense memory cell data selected from the plurality of memory cells, and a control signal generating unit configured to generate a sensing enable signal that activates the sense amplifier unit, and interface with the logic circuit.

9. The integrated circuit of claim 8, wherein the control signal generating unit is configured to receive a read-enable signal having the first power supply voltage level from the logic circuit, and convert a level of the read-enable signal to a level of the sensing enable signal having the second power supply voltage level.

10. A decoder comprising:

a logic gate configured to decode a plurality of first input signals having a first power supply voltage level and generate a first output signal at an output node, the first output signal having a second power supply voltage level different from the first power supply voltage level; and

an inverter configured to invert the first output signal and generate a second output signal at the second power supply voltage level,

wherein the decoder is configured to receive a first clock signal configured to control precharging the output node at a first logic level of the first clock signal and evaluate the output node at a second logic level of the first clock signal, and

wherein the second output signal is received at the logic gate.

11. The decoder of claim 10, further comprising:

a latch circuit configured to operate at the first power supply voltage level, latch a plurality of second input signals and provide the plurality of first input signals with the plurality of latched second input signals.

12. The decoder of claim 11, wherein the latch circuit comprises:

a plurality of latches configured to latch the plurality of second input signals at a first logic level of a second clock signal and provide the plurality of first input signals with the plurality of latched second input signals at a second logic level of the second clock signal.

13. The decoder of claim 12, wherein the second clock signal operates at the first power supply voltage level, the first clock signal operates at the second power supply voltage level and the second clock signal is a buffered clock signal of the first clock signal.

14. The decoder of claim 10, wherein the logic gate comprises:

a first PMOS transistor connected to a second power supply voltage which supplies the second power supply voltage level, and configured to be controlled by the second output signal;

a second PMOS transistor connected between the first PMOS transistor and the output node, and configured to be controlled by the first input signals at the first power supply voltage level;

a third PMOS transistor connected to the second power supply voltage, and configured to be controlled by the first clock signal; and

first and second NMOS transistors serially connected between the output node and a ground voltage, and configured to be respectively controlled by the first input signals and the first clock signal.

15. The decoder of claim 10, wherein the logic gate comprises a transistor configured to prohibit the output node from being supplied with the second power supply voltage level when the output node is at a logic low level at the second logic level of the first clock signal.

16. A memory comprising:

an address decoder configured to decode a plurality of address input signals at a first power supply voltage level and generate a first address decoding signal at an output node at a second power supply voltage level different from the first power supply voltage level; and

an inverter configured to invert the first address decoding signal and generate a second address decoding signal at the second power supply voltage level,

wherein the memory is configured to receive a first clock signal configured to control precharging the output node at a first phase of the first clock signal and evaluate the output node at a second phase of the first clock signal, and

wherein the second address decoding signal is received at a logic gate.

17. The memory of claim 16, further comprising:

a memory array having a plurality of memory cells each of which is connected to a pair of bit-lines, a sense amplifier unit connected to the bit-lines and configured to sense memory cell data selected from the plurality of memory cells, and a control signal generating unit configured to generate a sensing enable signal that activates the sense amplifier unit, wherein the memory array is supplied with the second power supply voltage level.

18. The memory of claim 17, further comprising:

an address latch circuit configured to operate at the first power supply voltage level, latch a plurality of second input signals and provide the plurality of first input signals with the plurality of latched second input signals.

19. The memory of claim 18, wherein the address latch circuit comprises:

a plurality of latches configured to latch the plurality of second input signals at a first phase of a second clock signal and provide the plurality of first input signals with the plurality of latched second input signals at a second phase of the second clock signal.

20. The memory of claim 19, wherein the second clock signal operates at the first power supply voltage level, the first clock signal operates at the second power supply voltage level and the second clock signal is a buffered clock signal of the first clock signal.

21. The memory of claim 16, wherein the logic gate comprises

a first PMOS transistor connected to a second power supply voltage which supplies the second power supply voltage level, and configured to be controlled by a second output signal;

a second PMOS transistor connected between the first PMOS transistor and the output node, and configured to be controlled by first input signals at the first power supply voltage level;

a third PMOS transistor connected to the second power supply voltage, and configured to be controlled by the first clock signal; and

first and second NMOS transistors serially connected between the first node and a ground voltage, and configured to be respectively controlled by the first input signals and the first clock signal.

22. The memory of claim 16, wherein the logic gate comprises a transistor configured to prohibit the output node from being supplied with the second power supply voltage level when the output node is at a logic low level at a second logic level of the first clock signal.

23. A method of processing data by an integrated circuit comprising a logic circuit and a memory circuit, the method comprising:

generating, by the logic circuit, control signals having a first power supply voltage level which are used to control the memory circuit, and transmitting the control signals to the memory circuit;

shifting, by the memory circuit, levels of the controls signals to a second power supply voltage level which is different from the first power supply voltage level; and

performing, by the memory circuit, read or write operations according to the control signals having the shifted levels.

24. The method of claim 23, wherein the second power supply voltage level is greater than the first power supply voltage level.

25. The method of claim 23, wherein the generating of the control signals comprises generating an address signal indicating a location of a memory to be accessed in the memory circuit, a read-enable signal indicating a read operation to be performed, and a write-enable signal indicating a write operation to be performed.

26. The method of claim 23, further comprising:

performing an address decoding operation simultaneously with the shifting when the control signals transmitted to the memory circuit comprise address signals.