MEMORY DEVICE AND METHOD FOR DRIVING MEMORY ARRAY THEREOF

• US 20140160861A1
• Filed: 12/07/2012
• Published: 06/12/2014
• Est. Priority Date: 12/07/2012
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Hsin-Wen
• Granted Patent: US 8,953,401 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read, and meanwhile use local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells.

Claims

1. A memory device comprising:

a bit line;

a bit line bar;

a write buffer;

a sense amplifier;

a column multiplexer for outputting data from the bit line and the bit line bar to the sense amplifier, and outputting data from the write buffer to the bit line and the bit line bar; and

a local voltage source configured to receive a working voltage and provide a high voltage lower than the working voltage to the bit line and the bit line bar.

2. The memory device of claim 1 where the local voltage source comprises:

a first NMOS transistor having;

a first end for receiving a working voltage;

a second end coupled to the bit line; and

a control end; and

a second NMOS transistor having;

a first end for receiving the working voltage;

a second end coupled to the bit line bar; and

a control end coupled to the control end of the first NMOS transistor.

3. A method for driving a memory array, the memory array comprising a plurality of columns of memory cells, each column of memory cells of the memory array being coupled to a local voltage source, a bit line, and a bit line bar, the method comprising:

providing a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read; and

using local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells when the memory cell is selected to be read.

4. The method of claim 3 further comprising:

providing the working voltage to one of the bit line and the bit line bar of the column of memory cells when the memory cell is selected to be written.

5. The method of claim 4 further comprising:

providing a low voltage lower than the working voltage to another one of the bit line and the bit line bar of the column of memory cells when the memory cell is selected to be written.

6. The method of claim 5 further comprising:

using the local voltage sources to pre-charge the bit lines and the bit line bars of the remaining columns of memory cells to the high voltages when the memory cell is selected to be written.

7. The method of claim 3 further comprising:

providing the high voltage to one of the bit line and the bit line bar of the column of memory cells when the memory cell is selected to be written.

8. The method of claim 7 further comprising:

providing a low voltage lower than the high voltage to another one of the bit line and the bit line bar of the column of memory cells when the memory cell is selected to be written.

9. The method of claim 8 further comprising:

using the local voltage sources to pre-charge the bit lines and the bit line bars of the remaining columns of memory cells to the high voltages when the memory cell is selected to be written.

10. A method for driving a memory array, the memory array comprising

a plurality of columns of memory cells, each column of memory cells of the columns of memory cells being coupled to a local voltage source, a bit line and a bit line bar, the local voltage source comprising a first NMOS transistor coupled between a working voltage and the bit line, and a second NMOS transistor coupled between the working voltage and the bit line bar, a control end of the first NMOS transistor being coupled to a control end of the second NMOS transistor, the method comprising:

providing a high voltage lower than the working voltage to one of the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be written; and

providing a low voltage lower than the working voltage to another one of the bit line and the bit line bar of the column of memory cells when the memory cell is selected to be written.

11. The method of claim 10 further comprising:

using local voltage sources coupled to remaining columns of memory cells of the columns of memory cells to pre-charge the bit lines and the bit line bars of the remaining columns of memory cells to the high voltage when the memory cell is selected to be written.