THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL, AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR

• US 20140167038A1
• Filed: 02/12/2014
• Published: 06/19/2014
• Est. Priority Date: 04/02/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Klaus Schmidt
• Inventors: AHN, Byung Du, LIM, Ji Hun, KIM, Gun Hee, LEE, Kyoung Won, LEE, Je Hun, GOTO, HIROSHI, MIKI, AYA, MORITA, SHINYA, KUGIMIYA, TOSHIHIRO, KIM, Yeon Hong, MO, Yeon Gon, KIM, Kwang Suk
• Granted Patent: US 9,553,201 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

Claims

1. A thin film transistor comprising:

a gate electrode;

a gate insulating layer positioned on or under the gate electrode;

a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other;

a source electrode connected to the second semiconductor; and

a drain electrode connected to the second semiconductor and facing the source electrode,

wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and

a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

2. The thin film transistor of claim 1, wherein

the first semiconductor and the second semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

3. The thin film transistor of claim 2, wherein

a content ratio of zinc (Zn) to tin (Sn) included in the first semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second semiconductor.

4. The thin film transistor of claim 3, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

5. The thin film transistor of claim 2, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

6. The thin film transistor of claim 1, wherein the first semiconductor and the second semiconductor include tin (Sn) and zinc, and

wherein a content ratio of zinc (Zn) to tin (Sn) included in the first semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second semiconductor.

7. The thin film transistor of claim 6, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

8. The thin film transistor of claim 1, wherein

etching rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

17. A thin film transistor array panel comprising the thin film transistor of claim 1.

9. A thin film transistor comprising:

a gate electrode;

a semiconductive layer overlapping the gate electrode with a gate insulating layer interposed between the gate electrode and the semiconductive layer, wherein the semiconductive layer includes a first semiconductor and a second semiconductor, the first semiconductor and the second semiconductor contacting each other;

a source electrode connected to the second semiconductor; and

a drain electrode connected to the second semiconductor and facing the source electrode,

wherein the first semiconductor and the second semiconductor include tin and zinc, and

wherein a content ratio of zinc (Zn) to tin (Sn) included in the first semiconductor is substantially the same as a content ratio of zinc (Zn) to tin (Sn) included in the second semiconductor.

10. The thin film transistor of claim 9, wherein

the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and

a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.

11. The thin film transistor of claim 10, wherein

the first semiconductor and the second semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

12. The thin film transistor of claim 11, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

13. The thin film transistor of claim 10, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

14. The thin film transistor of claim 9, wherein

the first semiconductor and the second semiconductor respectively include indium (In)-tin (Sn)-zinc (Zn) oxide (IZTO).

15. The thin film transistor of claim 14, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.

16. The thin film transistor of claim 9, wherein

etch rates of the first semiconductor and the second semiconductor in a same etchant are substantially the same.