LINEAR RESISTOR WITH HIGH RESOLUTION AND BANDWIDTH

• US 20140167821A1
• Filed: 12/19/2012
• Published: 06/19/2014
• Est. Priority Date: 12/19/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Zuoguo, Yang, Yong
• Granted Patent: US 9,484,888 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03H 11/245 using field-effect transistor

Abstract

Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.

Claims

1. An apparatus comprising:

a first voltage follower;

a second voltage follower; and

a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.

2. The apparatus of claim 1, wherein the first and second voltage followers have corresponding first and second inputs coupled to either non-gate terminals of the pass-gate.

3. The apparatus of claim 2, wherein the first voltage follower comprises at least two n-type transistors coupled in parallel to one another.

4. The apparatus of claim 3, wherein gate terminals of the at least two n-type transistors are coupled to corresponding first and second inputs respectively, wherein source terminals of the at least two n-type transistors are coupled to the output of the first voltage follower, and wherein drain terminals of the at least two n-type transistors are coupled to a power supply node.

5. The apparatus of claim 1 further comprises a current mirror coupled to the outputs of the first and second voltage followers.

6. The apparatus of claim 1, wherein the first voltage follower is a p-type voltage follower, and wherein the second voltage follower is an n-type voltage follower.

7. The apparatus of claim 2, wherein the first voltage follower comprises an OPAMP with an output coupled to a p-type transistor.

8. The apparatus of claim 7, wherein the p-type transistor is diode connected.

9. The apparatus of claim 7, wherein the OPAMP includes a first input coupled to the first and second inputs of the first voltage follower via resistive elements, and wherein the OPAMP includes a second input coupled to the output of the OPAMP.

10. The apparatus of claim 7, wherein the OPAMP includes four input terminals, wherein the first and second inputs are coupled to two positive terminals of the OPAMP, and wherein the output of the OPAMP is coupled to two negative terminals of the OPAMP.

11. The apparatus of claim 2, wherein the second voltage follower comprises at least two p-type transistors coupled in parallel to one another.

12. The apparatus of claim 11, wherein gate terminals of the at least two p-type transistors are coupled to corresponding first and second inputs respectively, wherein source terminals of the at least two n-type transistors are coupled to the output of the second voltage follower, and wherein drain terminals of the at least two p-type transistors are coupled to a ground node.

19. The apparatus of claim 1, wherein the first and second voltage followers have corresponding first and second inputs coupled to either non-gate terminals of the pass-gate.

20. The system of claim 19, wherein gate terminals of the at least two n-type transistors are coupled to corresponding first and second inputs respectively, wherein source terminals of the at least two n-type transistors are coupled to the output of the first voltage follower, and wherein drain terminals of the at least two n-type transistors are coupled to a power supply node.

13. An apparatus comprising:

a Continuous-Time Linear Equalizer (CTLE) with programmable linear resistor, the programmable linear resistor comprising;

a first input;

a second input;

a first voltage follower;

a second voltage follower; and

a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower, and wherein the first and second inputs are coupled to either non-gate terminals of the pass-gate.

14. The apparatus of claim 13, wherein the first voltage follower is a p-type voltage follower, and wherein the second voltage follower is an n-type voltage follower.

15. The apparatus of claim 13, wherein the first and second voltage followers have corresponding first and second inputs coupled to the either non-gate terminals of the pass-gate.

16. The apparatus of claim 13, wherein the programmable linear resistor further comprises a current mirror coupled to the outputs of the first and second voltage followers.

17. A system comprising:

a memory unit;

a processor, coupled to the memory unit, the processor including an receiver with a programmable resistor comprising;

a first voltage follower;

a second voltage follower; and

a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower; and

a wireless interface for allowing the processor to communicate with another device.

18. The system of claim 17 further comprises a display unit.